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[PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext i
From: |
Rajnesh Kanwal |
Subject: |
[PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled |
Date: |
Fri, 26 May 2023 17:23:05 +0100 |
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
target/riscv/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db0875fb43..269a094f42 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1280,6 +1280,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_pmu_timer_cb, cpu);
}
}
+
+ /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
+ if (riscv_has_ext(env, RVH)) {
+ env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
+ }
#endif
riscv_cpu_finalize_features(cpu, &local_err);
--
2.25.1
- [PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support, Rajnesh Kanwal, 2023/05/26
- [PATCH v2 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Rajnesh Kanwal, 2023/05/26
- [PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Rajnesh Kanwal, 2023/05/26
- [PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled,
Rajnesh Kanwal <=
- [PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Rajnesh Kanwal, 2023/05/26
- [PATCH v2 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/05/26
- [PATCH v2 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/05/26