Re: How to enable Zicsr extension support on qemu-riscv32?

[Daniel Henrique Barboza]

Tommy,

I tried it out and yeah, the SIGILL happens but it's supposed to happen. The
reason is that 'misa' is a CSR that is not available for linux-user mode. If
you try the same example with an available CSR it works.

I posted this info with a little more detail in the riscv-gnu-toolchain issue
you mentioned. Opening a gitlab QEMU issue is not necessary.


Thanks,


Daniel

On 6/25/23 20:24, Daniel Henrique Barboza wrote:
> Hi,
>
> On 6/25/23 17:44, Tommy Murphy wrote:
> > Hi there
> >
> > I've tried searching to find an answer to this question but with no success so 
> > far unfortunately.
> >
> > The issue is discussed here: 
> > https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1278#issuecomment-1606108826
> >  
> > <https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1278#issuecomment-1606108826>
> >
> > But the gist is that I can configure, build and use `qemu-riscv32` to run a simple bare 
> > metal "hello world" program fine.
> > But if I add a CSR read instruction to it (e.g. `asm("csrr t0, misa");`) then I 
> > get Illegal Instruction.
> >
> > This is the case even if I use `qemu-riscv32 -cpu rv32,Zicsr=on hello.exe`.
> >
> > How can I configure/invoke `qemu-riscv32` so that I can emulate CSR 
> > instructions?
>
> rv32 already has Zicsr support enabled by default. There might a bug
> somewhere.
>
> Please file a gitlab bug (https://gitlab.com/qemu-project/qemu/-/issues) and
> we'll take a look. Don't forget to mention that you managed to reproduce the
> SIGILL using upstream QEMU as you mentioned in the toolchain bug. Thanks,
>
>
> Daniel
>
> > Thanks a lot
> >
> > Regards
> > Tommy