Re: [PATCH v14 0/7] Pointer Masking update for Zjpm v1.0

[Alistair Francis]

On Tue, Dec 17, 2024 at 6:57 PM <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Hi,
>
> Rebased and addressed Alistair's comments on code style.
>
> Thanks
>
> [v13]:
> Rebased and addressed Daniel's comments about the return type of the helper.
>
> Thanks
>
> [v12]:
> Rebased and addressed Richard's comments about proper masking virtualized 
> accesses.
>
> Thanks
>
> [v11]:
> As suggested on the mailing list by Daniel, I'm resubmitting this series and 
> keeping the original versioning number.
> So that makes this one v11 and previous - v10.
> Also I applied previously issues reviewed-by tags on some of the patches that 
> were present in v9 series, but only for the code, that didn't change much.
> For the others I'd really like to have them reviewed as there were a lot of 
> comments on v9 series.
> Also rebased on the current upstream.
>
> Thanks
>
> [v10]:
> I've rebased this patch series and addressed Richard's and Daniel's comments.
> Thanks
>
> [v0]:
> As Pointer Masking is finally ratified, these patches intend to update the 
> existing code to the final version.
> These patches have been submitted previously and I tried to address all the 
> suggestions, but I'd suggest to review them from the clean slate and then 
> finally push them to the repo.
> Thanks.
>
> Alexey Baturo (7):
>   target/riscv: Remove obsolete pointer masking extension code.
>   target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part
>     of Zjpm v1.0
>   target/riscv: Add helper functions to calculate current number of
>     masked bits for pointer masking
>   target/riscv: Add pointer masking tb flags
>   target/riscv: Update address modify functions to take into account
>     pointer masking
>   target/riscv: Apply pointer masking for virtualized memory accesses
>   target/riscv: Enable updates for pointer masking variables and thus
>     enable pointer masking extension

This is all reviewed, but doesn't apply to
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
unfortunatley. Do you mind rebasing and hopefully this should then be
merged :)

Alistair

>
>  target/riscv/cpu.c           |  19 +-
>  target/riscv/cpu.h           |  50 ++---
>  target/riscv/cpu_bits.h      |  91 +--------
>  target/riscv/cpu_cfg.h       |   3 +
>  target/riscv/cpu_helper.c    | 128 +++++++++----
>  target/riscv/csr.c           | 357 +++--------------------------------
>  target/riscv/internals.h     |  54 ++++++
>  target/riscv/machine.c       |  17 +-
>  target/riscv/op_helper.c     |  16 +-
>  target/riscv/pmp.c           |  14 +-
>  target/riscv/pmp.h           |   1 +
>  target/riscv/tcg/tcg-cpu.c   |   5 +-
>  target/riscv/translate.c     |  47 ++---
>  target/riscv/vector_helper.c |   5 -
>  14 files changed, 257 insertions(+), 550 deletions(-)
>
> --
> 2.39.5
>