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[PATCH v12 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig
From: |
frank . chang |
Subject: |
[PATCH v12 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig |
Date: |
Mon, 6 Jan 2025 13:43:31 +0800 |
From: Tommy Wu <tommy.wu@sifive.com>
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fe0c4173d2..28b43932db 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -129,6 +129,7 @@ struct RISCVCPUConfig {
bool ext_ssaia;
bool ext_sscofpmf;
bool ext_smepmp;
+ bool ext_smrnmi;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool rvv_vl_half_avl;
--
2.34.1
- [PATCH v12 0/6] Add Smrnmi support, frank . chang, 2025/01/06
- [PATCH v12 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig,
frank . chang <=
- [PATCH v12 2/6] target/riscv: Add Smrnmi CSRs, frank . chang, 2025/01/06
- [PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception, frank . chang, 2025/01/06
- [PATCH v12 4/6] target/riscv: Add Smrnmi mnret instruction, frank . chang, 2025/01/06
- [PATCH v12 5/6] target/riscv: Add Smrnmi cpu extension, frank . chang, 2025/01/06
- [PATCH v12 6/6] target/riscv: Add Zicfilp support for Smrnmi, frank . chang, 2025/01/06
- Re: [PATCH v12 0/6] Add Smrnmi support, Alistair Francis, 2025/01/06