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Re: [qemu-s390x] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER
From: |
David Hildenbrand |
Subject: |
Re: [qemu-s390x] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK |
Date: |
Mon, 6 May 2019 11:42:22 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 02.05.19 16:10, David Hildenbrand wrote:
> Let's return the cc value directly via cpu_env. Unfortunately there
> isn't a simple way to calculate the value lazily - one would have to
> calculate and store e.g. the population count of the mask and the
> result so it can be evaluated in a cc helper.
>
> But as VTM only sets the cc, we can assume the value will be needed soon
> either way.
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: David Hildenbrand <address@hidden>
> ---
> target/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 11 +++++++++++
> target/s390x/vec_int_helper.c | 18 ++++++++++++++++++
> 4 files changed, 32 insertions(+)
>
> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
> index 2cb1f369bd..7755a96c33 100644
> --- a/target/s390x/helper.h
> +++ b/target/s390x/helper.h
> @@ -209,6 +209,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr,
> cptr, i64, i32)
> DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
> DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
> DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
> +DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
>
> #ifndef CONFIG_USER_ONLY
> DEF_HELPER_3(servc, i32, env, i64, i64)
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index a52db41388..e61475bdc4 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -1188,6 +1188,8 @@
> F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
> /* VECTOR SUM ACROSS WORD */
> F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
> +/* VECTOR TEST UNDER MASK */
> + F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
>
> #ifndef CONFIG_USER_ONLY
> /* COMPARE AND SWAP AND PURGE */
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 23eca2b332..e12ba00a13 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t
> reg, TCGv_i64 enr,
> #define gen_gvec_2i_ool(v1, v2, c, data, fn) \
> tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> c, 16, 16, data, fn)
> +#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
> + tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> + ptr, 16, 16, data, fn)
> #define gen_gvec_3(v1, v2, v3, gen) \
> tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> vec_full_reg_offset(v3), 16, 16, gen)
> @@ -2338,3 +2341,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps
> *o)
> tcg_temp_free_i32(tmp);
> return DISAS_NEXT;
> }
> +
> +static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
> +{
> + gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
> + cpu_env, 0, gen_helper_gvec_vtm);
> + set_cc_static(s);
> + return DISAS_NEXT;
> +}
> diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
> index 09137dab99..3e8837e09a 100644
> --- a/target/s390x/vec_int_helper.c
> +++ b/target/s390x/vec_int_helper.c
> @@ -583,3 +583,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2,
> const void *v3, \
> }
> DEF_VSCBI(8)
> DEF_VSCBI(16)
> +
> +void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
> + uint32_t desc)
> +{
> + S390Vector tmp;
> +
> + s390_vec_and(&tmp, v1, v2);
> + if (s390_vec_is_zero(&tmp)) {
> + /* Selected bits all zeros; or all mask bits zero */
> + env->cc_op = 0;
> + } else if (s390_vec_equal(&tmp, v2)) {
> + /* Selected bits all ones */
> + env->cc_op = 3;
> + } else {
> + /* Selected bits a mix of zeros and ones */
> + env->cc_op = 1;
> + }
> +}
>
This hunk got lost in follow-up patches:
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 09137dab99..68eaae407b 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -28,6 +28,19 @@ static void s390_vec_xor(S390Vector *res, const
S390Vector *a,
res->doubleword[1] = a->doubleword[1] ^ b->doubleword[1];
}
+static void s390_vec_and(S390Vector *res, const S390Vector *a,
+ const S390Vector *b)
+{
+ res->doubleword[0] = a->doubleword[0] & b->doubleword[0];
+ res->doubleword[1] = a->doubleword[1] & b->doubleword[1];
+}
+
+static bool s390_vec_equal(const S390Vector *a, const S390Vector *b)
+{
+ return a->doubleword[0] == b->doubleword[0] &&
+ a->doubleword[1] == b->doubleword[1];
+}
+
static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t
count)
{
uint64_t tmp;
--
Thanks,
David / dhildenb
- [qemu-s390x] [PATCH v3 33/40] s390x/tcg: Implement VECTOR SUBTRACT, (continued)
- [qemu-s390x] [PATCH v3 33/40] s390x/tcg: Implement VECTOR SUBTRACT, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 34/40] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 35/40] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 36/40] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 37/40] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 38/40] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 39/40] s390x/tcg: Implement VECTOR SUM ACROSS WORD, David Hildenbrand, 2019/05/02
- [qemu-s390x] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK, David Hildenbrand, 2019/05/02
- Re: [qemu-s390x] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK,
David Hildenbrand <=