Re: [PATCH v6 2/2] target/s390x: Store r1/r2 for page-translation exceptions during MVPG

[Richard Henderson]

On 3/11/21 1:44 PM, David Hildenbrand wrote:
> The PoP states:
>
>      When EDAT-1 does not apply, and a program interruption due to a
>      page-translation exception is recognized by the MOVE PAGE
>      instruction, the contents of the R1 field of the instruction are
>      stored in bit positions 0-3 of location 162, and the contents of
>      the R2 field are stored in bit positions 4-7.
>
>      If [...] an ASCE-type, region-first-translation,
>      region-second-translation, region-third-translation, or
>      segment-translation exception was recognized, the contents of
>      location 162 are unpredictable.
>
> So we have to write r1/r2 into the lowcore on page-translation
> exceptions. Simply handle all exceptions inside our mvpg helper now.
>
> Signed-off-by: David Hildenbrand<david@redhat.com>
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~