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[PATCH 06/10] tcg/s390x: Create tgen_cmp2 to simplify movcond
From: |
Richard Henderson |
Subject: |
[PATCH 06/10] tcg/s390x: Create tgen_cmp2 to simplify movcond |
Date: |
Thu, 24 Feb 2022 05:43:29 -1000 |
Return both regular and inverted condition codes from tgen_cmp2.
This lets us choose after the fact which comparision we want.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 58ebb925d9..18b8ca3132 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -1376,10 +1376,11 @@ static void tgen_xori(TCGContext *s, TCGType type,
TCGReg dest, uint64_t val)
}
}
-static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
- TCGArg c2, bool c2const, bool need_carry)
+static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
+ TCGArg c2, bool c2const, bool need_carry, int *inv_cc)
{
bool is_unsigned = is_unsigned_cond(c);
+ TCGCond inv_c = tcg_invert_cond(c);
S390Opcode op;
if (c2const) {
@@ -1390,6 +1391,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond
c, TCGReg r1,
} else {
tcg_out_insn(s, RRE, LTGR, r1, r1);
}
+ *inv_cc = tcg_cond_to_ltr_cond[inv_c];
return tcg_cond_to_ltr_cond[c];
}
}
@@ -1453,9 +1455,17 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond
c, TCGReg r1,
}
exit:
+ *inv_cc = tcg_cond_to_s390_cond[inv_c];
return tcg_cond_to_s390_cond[c];
}
+static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
+ TCGArg c2, bool c2const, bool need_carry)
+{
+ int inv_cc;
+ return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc);
+}
+
static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
{
@@ -1556,20 +1566,19 @@ static void tgen_movcond(TCGContext *s, TCGType type,
TCGCond c, TCGReg dest,
TCGReg c1, TCGArg c2, int c2const,
TCGArg v3, int v3const)
{
- int cc;
+ int cc, inv_cc;
+
+ cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc);
+
if (HAVE_FACILITY(LOAD_ON_COND)) {
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
if (v3const) {
tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc);
} else {
tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc);
}
} else {
- c = tcg_invert_cond(c);
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
-
/* Emit: if (cc) goto over; dest = r3; over: */
- tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+ tcg_out_insn(s, RI, BRC, inv_cc, (4 + 4) >> 1);
tcg_out_insn(s, RRE, LGR, dest, v3);
}
}
--
2.25.1
- [PATCH 00/10] tcg/s390x: updates for mie2 and mie3, Richard Henderson, 2022/02/24
- [PATCH 01/10] tcg/s390x: Distinguish RRF-a and RRF-c formats, Richard Henderson, 2022/02/24
- [PATCH 02/10] tcg/s390x: Distinguish RIE formats, Richard Henderson, 2022/02/24
- [PATCH 03/10] tcg/s390x: Support MIE2 multiply single instructions, Richard Henderson, 2022/02/24
- [PATCH 06/10] tcg/s390x: Create tgen_cmp2 to simplify movcond,
Richard Henderson <=
- [PATCH 05/10] tcg/s390x: Support MIE3 logical operations, Richard Henderson, 2022/02/24
- [PATCH 04/10] tcg/s390x: Support MIE2 MGRK instruction, Richard Henderson, 2022/02/24
- [PATCH 08/10] tcg/s390x: Use tgen_movcond_int in tgen_clz, Richard Henderson, 2022/02/24
- [PATCH 07/10] tcg/s390x: Support SELGR instruction in MOVCOND, Richard Henderson, 2022/02/24
- [PATCH 09/10] tcg/s390x: Use vector ctz for integer ctz, Richard Henderson, 2022/02/24
- [PATCH 10/10] tcg/s390x: Implement ctpop operation, Richard Henderson, 2022/02/24