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[PATCH v2 4/7] target/s390x: vxeh2: vector {load, store} elements revers
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From: |
David Miller |
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Subject: |
[PATCH v2 4/7] target/s390x: vxeh2: vector {load, store} elements reversed |
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Date: |
Sun, 6 Mar 2022 21:03:24 -0500 |
Signed-off-by: David Miller <dmiller423@gmail.com>
---
target/s390x/helper.h | 4 ++-
target/s390x/tcg/insn-data.def | 4 +++
target/s390x/tcg/translate_vx.c.inc | 39 +++++++++++++++++++++++++++++
target/s390x/tcg/vec.h | 24 ++++++++++++++++++
target/s390x/tcg/vec_helper.c | 31 +++++++++++++++++++++++
5 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index a36308d651..933921a87c 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -129,6 +129,9 @@ DEF_HELPER_FLAGS_3(probe_write_access, TCG_CALL_NO_WG,
void, env, i64, i64)
/* === Vector Support Instructions === */
DEF_HELPER_FLAGS_4(gvec_vbperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
+DEF_HELPER_FLAGS_4(vler, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
+DEF_HELPER_FLAGS_4(vster, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
+DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
DEF_HELPER_FLAGS_4(gvec_vpk16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vpk32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vpk64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
@@ -145,7 +148,6 @@ DEF_HELPER_5(gvec_vpkls_cc16, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_5(gvec_vpkls_cc32, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr,
i32)
-DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
/* === Vector Integer Instructions === */
DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x/tcg/insn-data.def
index 1bfe88a4ac..3a7f15a0b5 100644
--- a/target/s390x/tcg/insn-data.def
+++ b/target/s390x/tcg/insn-data.def
@@ -1037,6 +1037,8 @@
E(0xe741, VLEIH, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_16, IF_VEC)
E(0xe743, VLEIF, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_32, IF_VEC)
E(0xe742, VLEIG, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)
+/* VECTOR LOAD ELEMENTS REVERSED */
+ F(0xe607, VLER, VRX, VE2, la2, 0, 0, 0, vler, 0, IF_VEC)
/* VECTOR LOAD GR FROM VR ELEMENT */
F(0xe721, VLGV, VRS_c, V, la2, 0, r1, 0, vlgv, 0, IF_VEC)
/* VECTOR LOAD LOGICAL ELEMENT AND ZERO */
@@ -1082,6 +1084,8 @@
E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)
E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)
E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)
+/* VECTOR STORE ELEMENTS REVERSED */
+ F(0xe60f, VSTER, VRX, VE2, la2, 0, 0, 0, vster, 0, IF_VEC)
/* VECTOR STORE MULTIPLE */
F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC)
/* VECTOR STORE WITH LENGTH */
diff --git a/target/s390x/tcg/translate_vx.c.inc
b/target/s390x/tcg/translate_vx.c.inc
index 60e1efdbfa..d543203e02 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -492,6 +492,26 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
+static DisasJumpType op_vler(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+
+ if (es < ES_16 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+ TCGv_i64 tes = tcg_const_i64(es & 0xf);
+
+ tcg_gen_addi_ptr(a0, cpu_env, vec_full_reg_offset(get_field(s, v1)));
+ gen_helper_vler(cpu_env, a0, o->addr1, tes);
+
+ tcg_temp_free_i64(tes);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
+
static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
{
const uint8_t es = get_field(s, m4);
@@ -976,6 +996,25 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
+static DisasJumpType op_vster(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ if (es < ES_16 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+ TCGv_i64 tes = tcg_const_i64(es);
+
+ tcg_gen_addi_ptr(a0, cpu_env, vec_full_reg_offset(get_field(s, v1)));
+ gen_helper_vster(cpu_env, a0, o->addr1, tes);
+
+ tcg_temp_free_i64(tes);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
+
static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
{
const uint8_t v3 = get_field(s, v3);
diff --git a/target/s390x/tcg/vec.h b/target/s390x/tcg/vec.h
index a6e361869b..5ea0446e4b 100644
--- a/target/s390x/tcg/vec.h
+++ b/target/s390x/tcg/vec.h
@@ -138,4 +138,28 @@ static inline void s390_vec_write_element(S390Vector *v,
uint8_t enr,
}
}
+static inline void s390_vec_reverse(uint64_t *vdst, uint64_t *vsrc, uint8_t es)
+{
+ const uint64_t l = vsrc[0], h = vsrc[1];
+
+ switch (es) {
+ case MO_8:
+ vdst[1] = bswap64(l);
+ vdst[0] = bswap64(h);
+ break;
+ case MO_16:
+ vdst[1] = hswap64(l);
+ vdst[0] = hswap64(h);
+ break;
+ case MO_32:
+ vdst[1] = wswap64(l);
+ vdst[0] = wswap64(h);
+ break;
+ case MO_64:
+ vdst[1] = l;
+ vdst[0] = h;
+ break;
+ }
+}
+
#endif /* S390X_VEC_H */
diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c
index ededf13cf0..96b488b6e0 100644
--- a/target/s390x/tcg/vec_helper.c
+++ b/target/s390x/tcg/vec_helper.c
@@ -212,3 +212,34 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1,
uint64_t addr,
*(S390Vector *)v1 = tmp;
}
}
+
+void HELPER(vler)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t es)
+{
+ uint64_t t0, t1;
+ t0 = cpu_ldq_data_ra(env, addr, GETPC());
+ addr = wrap_address(env, addr + 8);
+ t1 = cpu_ldq_data_ra(env, addr, GETPC());
+
+ if (MO_64 == es) {
+ s390_vec_write_element64(v1, 1, t0);
+ s390_vec_write_element64(v1, 0, t1);
+ } else {
+ S390Vector tmp = {};
+ s390_vec_write_element64(&tmp, 0, t0);
+ s390_vec_write_element64(&tmp, 1, t1);
+ s390_vec_reverse(v1, &tmp, (uint8_t)es);
+ }
+}
+
+void HELPER(vster)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t es)
+{
+ S390Vector tmp = {};
+ /* Probe write access before actually modifying memory */
+ probe_write_access(env, addr, 16, GETPC());
+
+ s390_vec_reverse(&tmp, v1, (uint8_t)es);
+
+ cpu_stq_data_ra(env, addr, tmp.doubleword[0], GETPC());
+ addr = wrap_address(env, addr + 8);
+ cpu_stq_data_ra(env, addr, tmp.doubleword[1], GETPC());
+}
--
2.34.1
- [PATCH v2 0/7] s390x/tcg: Implement Vector-Enhancements Facility 2, David Miller, 2022/03/06
- [PATCH v2 1/7] target/s390x: vxeh2: vector convert short/32b, David Miller, 2022/03/06
- [PATCH v2 3/7] target/s390x: vxeh2: vector shift {double by bit, left, right {logical, arithmetic}}, David Miller, 2022/03/06
- [PATCH v2 4/7] target/s390x: vxeh2: vector {load, store} elements reversed,
David Miller <=
- [PATCH v2 7/7] tests/tcg/s390x: Tests for Vector Enhancements Facility 2, David Miller, 2022/03/06
- [PATCH v2 6/7] target/s390x: add S390_FEAT_VECTOR_ENH2 to cpu max, David Miller, 2022/03/06
- [PATCH v2 2/7] target/s390x: vxeh2: vector string search, David Miller, 2022/03/06
- [PATCH v2 5/7] target/s390x: vxeh2: vector {load, store} reversed elements [and {zero, replicate}], David Miller, 2022/03/06