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[Qemu-stable] [PATCH 24/99] hw/intc/arm_gicv3: Fix APxR<n> register disp
From: |
Michael Roth |
Subject: |
[Qemu-stable] [PATCH 24/99] hw/intc/arm_gicv3: Fix APxR<n> register dispatching |
Date: |
Mon, 23 Jul 2018 15:16:33 -0500 |
From: Jan Kiszka <address@hidden>
There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Cc: address@hidden
Signed-off-by: Jan Kiszka <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
(cherry picked from commit 887aae10f6150dfdc71c45d7588e8efe6c144019)
Signed-off-by: Michael Roth <address@hidden>
---
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 26f5eeda94..554be25cb7 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -431,7 +431,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value = cs->ich_apr[grp][regno];
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -443,7 +443,7 @@ static void icv_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
@@ -1465,7 +1465,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
uint64_t value;
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
return icv_ap_read(env, ri);
@@ -1487,7 +1487,7 @@ static void icc_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
icv_ap_write(env, ri, value);
@@ -2296,7 +2296,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value;
value = cs->ich_apr[grp][regno];
@@ -2309,7 +2309,7 @@ static void ich_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
--
2.17.1
- [Qemu-stable] [PATCH 17/99] lm32: take BQL before writing IP/IM register, (continued)
- [Qemu-stable] [PATCH 17/99] lm32: take BQL before writing IP/IM register, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 16/99] iotests: Add test for -U/force-share conflicts, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 18/99] raw: Check byte range uniformly, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 19/99] s390x/css: disabled subchannels cannot be status pending, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 20/99] pc-bios/s390-ccw: struct tpi_info must be declared as aligned(4), Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 01/99] tests: fix tpm-crb tpm-tis tests race, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 21/99] virtio-ccw: common reset handler, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 22/99] s390x/ccw: make sure all ccw devices are properly reset, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 23/99] console: Avoid segfault in screendump, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 25/99] intel-iommu: send PSI always even if across PDEs, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 24/99] hw/intc/arm_gicv3: Fix APxR<n> register dispatching,
Michael Roth <=
- [Qemu-stable] [PATCH 26/99] intel-iommu: remove IntelIOMMUNotifierNode, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 27/99] intel-iommu: add iommu lock, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 30/99] intel-iommu: pass in address space when page walk, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 29/99] intel-iommu: introduce vtd_page_walk_info, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 28/99] intel-iommu: only do page walk for MAP notifiers, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 02/99] device_tree: Increase FDT_MAX_SIZE to 1 MiB, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 31/99] intel-iommu: trace domain id during page walk, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 34/99] arm_gicv3_kvm: increase clroffset accordingly, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 33/99] intel-iommu: rework the page walk logic, Michael Roth, 2018/07/23
- [Qemu-stable] [PATCH 32/99] util: implement simple iova tree, Michael Roth, 2018/07/23