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Re: [Qemu-trivial] [Qemu-arm] [PATCH] arm/translate-a64: mark path as un


From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-trivial] [Qemu-arm] [PATCH] arm/translate-a64: mark path as unreachable to eliminate warning
Date: Wed, 8 Nov 2017 09:37:26 -0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0

On 11/07/2017 05:46 PM, Emilio G. Cota wrote:
> Fixes the following warning when compiling with gcc 5.4.0 with -O1
> optimizations and --enable-debug:
> 
> target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
> target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used 
> uninitialized in this function [-Werror=maybe-uninitialized]
>      if (!post_index) {
>         ^
> target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
>      bool post_index;
>           ^
> target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used 
> uninitialized in this function [-Werror=maybe-uninitialized]
>      if (writeback) {
>         ^
> target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
>      bool writeback;
>           ^
> 
> Note that idx comes from selecting 2 bits, and therefore its value
> can be at most 3.
> 
> Signed-off-by: Emilio G. Cota <address@hidden>

Acked-by: Philippe Mathieu-Daudé <address@hidden>

> ---
>  target/arm/translate-a64.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index caca05a..625ef2d 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -2340,28 +2340,30 @@ static void disas_ldst_reg_imm9(DisasContext *s, 
> uint32_t insn,
>      switch (idx) {
>      case 0:
>      case 2:
>          post_index = false;
>          writeback = false;
>          break;
>      case 1:
>          post_index = true;
>          writeback = true;
>          break;
>      case 3:
>          post_index = false;
>          writeback = true;
>          break;
> +    default:
> +        g_assert_not_reached();
>      }
>  
>      if (rn == 31) {
>          gen_check_sp_alignment(s);
>      }
>      tcg_addr = read_cpu_reg_sp(s, rn, 1);
>  
>      if (!post_index) {
>          tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
>      }
>  
>      if (is_vector) {
>          if (is_store) {
>              do_fp_st(s, rt, tcg_addr, size);
> 



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