Re: [Qemu-trivial] [Qemu-devel] [PATCH v2] hw/char/escc: Lower irq when transmit buffer is filled

[Stephen Checkoway]

> On Apr 18, 2019, at 08:13, Philippe Mathieu-Daudé <address@hidden> wrote:
> 
> On 4/17/19 2:50 AM, Stephen Checkoway wrote:
>> The SCC/ESCC will briefly stop asserting an interrupt when the
>> transmit FIFO is filled.
>> 
>> This code doesn't model the transmit FIFO/shift register so the
>> pending transmit interrupt is never deasserted which means that an
>> edge-triggered interrupt controller will never see the low-to-high
>> transition it needs to raise another interrupt. The practical
>> consequence of this is that guest firmware with an interrupt service
>> routine for the ESCC that does not send all of the data it has
>> immediately will stop sending data if the following sequence of
>> events occurs:
>> 1. Disable processor interrupts
>> 2. Write a character to the ESCC
>> 3. Add additional characters to a buffer which is drained by the ISR
>> 4. Enable processor interrupts
>> 
>> In this case, the first character will be sent, the interrupt will
>> fire and the ISR will output the second character. Since the pending
>> transmit interrupt remains asserted, no additional interrupts will
>> ever fire.
> 
> You might want to add a line expliciting the chipset model which forced
> you to do that patch (Z85C30).

Done.

Thanks for looking at this.

-- 
Stephen Checkoway