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Re: [PATCH 2/3] hw/mips/gt64xxx: Remove dynamic field width from trace e

From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 2/3] hw/mips/gt64xxx: Remove dynamic field width from trace event
Date: Fri, 8 Nov 2019 15:36:52 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 
On 11/8/19 3:26 PM, Philippe Mathieu-Daudé wrote:

Since not all trace backends support dynamic field width in
format (dtrace via stap does not), replace by a static field
width instead.

Reported-by: Eric Blake <address@hidden>
Buglink: https://bugs.launchpad.net/qemu/+bug/1844817
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
  hw/mips/gt64xxx_pci.c | 34 +++++++++++++++++-----------------
  hw/mips/trace-events  |  4 ++--
  2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 5cab9c1ee1..f427793360 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -464,7 +464,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_GUEST_ERROR,
                        "gt64120: Read-only register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);


Wrong replacement :( I'll respin.


          break;
/* CPU Sync Barrier */ 
@@ -474,7 +474,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_GUEST_ERROR,
                        "gt64120: Read-only register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
/* SDRAM and Device Address Decode */ 
@@ -516,7 +516,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_UNIMP,
                        "gt64120: Unimplemented device register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
/* ECC */ 
@@ -529,7 +529,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_GUEST_ERROR,
                        "gt64120: Read-only register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
/* DMA Record */ 
@@ -566,7 +566,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_UNIMP,
                        "gt64120: Unimplemented DMA register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
/* Timer/Counter */ 
@@ -579,7 +579,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_UNIMP,
                        "gt64120: Unimplemented timer register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
/* PCI Internal */ 
@@ -623,7 +623,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_UNIMP,
                        "gt64120: Unimplemented timer register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
      case GT_PCI0_CFGADDR:
          phb->config_reg = val & 0x80fffffc;
@@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          /* not really implemented */
          s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
          s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
-        trace_gt64120_write("INTRCAUSE", size << 1, val);
+        trace_gt64120_write("INTRCAUSE", size << 3, val);
          break;
      case GT_INTRMASK:
          s->regs[saddr] = val & 0x3c3ffffe;
-        trace_gt64120_write("INTRMASK", size << 1, val);
+        trace_gt64120_write("INTRMASK", size << 3, val);
          break;
      case GT_PCI0_ICMASK:
          s->regs[saddr] = val & 0x03fffffe;
-        trace_gt64120_write("ICMASK", size << 1, val);
+        trace_gt64120_write("ICMASK", size << 3, val);
          break;
      case GT_PCI0_SERR0MASK:
          s->regs[saddr] = val & 0x0000003f;
-        trace_gt64120_write("SERR0MASK", size << 1, val);
+        trace_gt64120_write("SERR0MASK", size << 3, val);
          break;
/* Reserved when only PCI_0 is configured. */ 
@@ -683,7 +683,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
          qemu_log_mask(LOG_GUEST_ERROR,
                        "gt64120: Illegal register write "
                        "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
      }
  }
@@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
      /* Interrupts */
      case GT_INTRCAUSE:
          val = s->regs[saddr];
-        trace_gt64120_read("INTRCAUSE", size << 1, val);
+        trace_gt64120_read("INTRCAUSE", size << 3, val);
          break;
      case GT_INTRMASK:
          val = s->regs[saddr];
-        trace_gt64120_read("INTRMASK", size << 1, val);
+        trace_gt64120_read("INTRMASK", size << 3, val);
          break;
      case GT_PCI0_ICMASK:
          val = s->regs[saddr];
-        trace_gt64120_read("ICMASK", size << 1, val);
+        trace_gt64120_read("ICMASK", size << 3, val);
          break;
      case GT_PCI0_SERR0MASK:
          val = s->regs[saddr];
-        trace_gt64120_read("SERR0MASK", size << 1, val);
+        trace_gt64120_read("SERR0MASK", size << 3, val);
          break;
/* Reserved when only PCI_0 is configured. */ 
@@ -960,7 +960,7 @@ static uint64_t gt64120_readl(void *opaque,
          qemu_log_mask(LOG_GUEST_ERROR,
                        "gt64120: Illegal register read "
                        "reg:0x03%x size:%u value:0x%0*x\n",
-                      saddr << 2, size, size << 1, val);
+                      saddr << 2, size, size << 3, val);
          break;
      }
diff --git a/hw/mips/trace-events b/hw/mips/trace-events 
index 75d4c73f2e..86a0213c77 100644
--- a/hw/mips/trace-events
+++ b/hw/mips/trace-events
@@ -1,4 +1,4 @@
  # gt64xxx.c
-gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s 
value:0x%0*" PRIx64
-gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s 
value:0x%0*" PRIx64
+gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s 
width:%d value:0x%08" PRIx64
+gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s 
width:%d value:0x%08" PRIx64
  gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" 
PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
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