On Tue, 25 Feb 2020 at 05:41, Jason Wang <address@hidden> wrote:
On 2020/2/25 上午10:59, Chen Qun wrote:
The current code causes clang static code analyzer generate warning:
hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
value = value & 0x0000000f;
^ ~~~~~~~~~~~~~~~~~~
hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
value = value & 0x000000fd;
^ ~~~~~~~~~~~~~~~~~~
According to the definition of the function, the two “value” assignments
should be written to registers.
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Chen Qun <address@hidden>
---
I'm not sure if this modification is correct, just from the function
definition, it is correct.
---
hw/net/imx_fec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 6a124a154a..92f6215712 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -855,13 +855,13 @@ static void imx_enet_write(IMXFECState *s, uint32_t
index, uint32_t value)
break;
case ENET_TGSR:
/* implement clear timer flag */
- value = value & 0x0000000f;
+ s->regs[index] = value & 0x0000000f;
break;
Hi; the datasheet for this SoC says that these bits
of the register are write-1-to-clear, so while this
is definitely a bug I don't think this is the right fix.
case ENET_TCSR0:
case ENET_TCSR1:
case ENET_TCSR2:
case ENET_TCSR3:
- value = value & 0x000000fd;
+ s->regs[index] = value & 0x000000fd;
break;
Here bit 7 is write-1-to-clear, though bits 0 and
2..5 are simple write-the-value.
case ENET_TCCR0:
case ENET_TCCR1:
Applied.
Could you drop this from your queue, please?
thanks
-- PMM