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RE: [PATCH v2] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()


From: Chenqun (kuhn)
Subject: RE: [PATCH v2] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
Date: Thu, 5 Mar 2020 11:04:46 +0000

>-----Original Message-----
>From: Chenqun (kuhn)
>Sent: Thursday, March 5, 2020 6:53 PM
>To: address@hidden; address@hidden
>Cc: address@hidden; Zhanghailiang
><address@hidden>; address@hidden;
>address@hidden; address@hidden; Chenqun (kuhn)
><address@hidden>; Euler Robot <address@hidden>
>Subject: [PATCH v2] hw/net/imx_fec: write TGSR and TCSR3 in
>imx_enet_write()
>
>The current code causes clang static code analyzer generate warning:
>hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
>        value = value & 0x0000000f;
>        ^       ~~~~~~~~~~~~~~~~~~
>hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
>        value = value & 0x000000fd;
>        ^       ~~~~~~~~~~~~~~~~~~
>
>According to the definition of the function, the two “value” assignments
>should be written to registers.
>
>Reported-by: Euler Robot <address@hidden>
>Signed-off-by: Chen Qun <address@hidden>
>---
>v1->v2:
>  The register 'ENET_TGSR' write-1-to-clear timer flag.
>  The register 'ENET_TCSRn' 7bit(TF) write-1-to-clear timer flag.
>---
> hw/net/imx_fec.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
>diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index
>6a124a154a..322cbdcc17 100644
>--- a/hw/net/imx_fec.c
>+++ b/hw/net/imx_fec.c
>@@ -855,13 +855,15 @@ static void imx_enet_write(IMXFECState *s,
>uint32_t index, uint32_t value)
>         break;
>     case ENET_TGSR:
>         /* implement clear timer flag */
>-        value = value & 0x0000000f;
>+        s->regs[index] ^= s->regs[index] & value;
>+        s->regs[index] &= 0x0000000f;
>
In "i.MX 6Dual/6Quad Applications Processor Reference Manual" documentation,  
the register  'ENET_TGSR'  all  fields TFn  is write-1-to-clear. 
It is described in detail as follows:
-------------------------------------------------------
Field          Description
-------------------------------------------------------
31–4         This field is reserved.  
-------------------------------------------------------
3              Copy Of Timer Flag For Channel 3
TF3         0 Timer Flag for Channel 3 is clear
                1 Timer Flag for Channel 3 is set
-------------------------------------------------------
2             Copy Of Timer Flag For Channel 2
TF2         0 Timer Flag for Channel 2 is clear
                1 Timer Flag for Channel 2 is set
-------------------------------------------------------
1              Copy Of Timer Flag For Channel 1
TF1         0 Timer Flag for Channel 1 is clear
                1 Timer Flag for Channel 1 is set
-------------------------------------------------------
0              Copy Of Timer Flag For Channel 0
TF0         0 Timer Flag for Channel 0 is clear
                1 Timer Flag for Channel 0 is set
------------------------------------------------------
>         break;
>     case ENET_TCSR0:
>     case ENET_TCSR1:
>     case ENET_TCSR2:
>     case ENET_TCSR3:
>-        value = value & 0x000000fd;
>+        s->regs[index] = (value & 0x00000080) ? (0x0000007d & value) :
>+                         (value & 0x000000fd);
>
The ENET_TCSRn field descriptions:
-------------------------------------------------------
Field          Description
-------------------------------------------------------
31–8      This field is reserved.
------------------------------------------------------
7              Timer Flag
TF            Sets when input capture or output compare occurs. 
                This flag is double buffered between the module clock and 1588 
clock domains. 
                When this field is 1, it can be cleared to 0 by writing 1to it.

                 0 Input Capture or Output Compare has not occurred
                 1 Input Capture or Output Compare has occurred
--------------------------------------------------------
6              Timer Interrupt Enable
TIE           0 Interrupt is disabled
                 1 Interrupt is enabled
--------------------------------------------------------
2-5           Timer Mode
                 ..................
--------------------------------------------------------
1              This field is reserved.
--------------------------------------------------------
0                Timer DMA Request Enable   
TDRE        0 DMA request is disabled
                   1 DMA request is enabled
--------------------------------------------------------

>         break;
>     case ENET_TCCR0:
>     case ENET_TCCR1:
>--
>2.23.0
>


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