Re: [PATCH] Fix MIPS add.s after 1ace099f2acb952eaaef0ba7725879949a7e4406

[Alexander Richardson]

Hi Philippe,

On Fri, 3 Jul 2020 at 19:40, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Alex,
>
> On 7/3/20 6:15 PM, Alex Richardson wrote:
> > After merging latest QEMU upstream into our CHERI fork, I noticed that
> > some of the FPU tests in our MIPS baremetal testsuite
>
> I understand by baremetal your soft core implementation running on
> a FPGA, right?
>
By baremetal I mean small test binaries running without a host OS.
The test suite was originally written for the CHERI FPGAs, but it also
supports various MIPS simulators, our executable formal model written
in sail and our fork of QEMU (https://github.com/CTSRD-CHERI/qemu).
Unfortunately it cannot be run with upstream QEMU as it requires a
special MTC0 instruction to dump register values in a textual format
to the logfile.

> > (https://github.com/CTSRD-CHERI/cheritest) started failing. It turns out
> > this commit accidentally changed add.s into a subtract.
>
> Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>")
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Thanks for your quick fix!
>
> Phil.
>
> > Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
> > ---
> >  target/mips/fpu_helper.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
> > index 7a3a61cab3..56beda49d8 100644
> > --- a/target/mips/fpu_helper.c
> > +++ b/target/mips/fpu_helper.c
> > @@ -1221,7 +1221,7 @@ uint32_t helper_float_add_s(CPUMIPSState *env,
> >  {
> >      uint32_t wt2;
> >
> > -    wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
> > +    wt2 = float32_add(fst0, fst1, &env->active_fpu.fp_status);
> >      update_fcr31(env, GETPC());
> >      return wt2;
> >  }
> >
>