simulavr-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[bug #66044] core->dataAddressMask not applied correctly


From: Georg-Johann Lay
Subject: [bug #66044] core->dataAddressMask not applied correctly
Date: Wed, 31 Jul 2024 06:37:01 -0400 (EDT)

URL:
  <https://savannah.nongnu.org/bugs/?66044>

                 Summary:  core->dataAddressMask not applied correctly
                   Group: Simulavr: an AVR simulator
               Submitter: gjlayde
               Submitted: Wed 31 Jul 2024 10:36:58 AM UTC
                Category: Simulation
                Severity: 3 - Normal
              Item Group: None
                  Status: None
                 Privacy: Public
             Assigned to: None
        Originator Email: 
             Open/Closed: Open
         Discussion Lock: Any
       Component Version: simulavr


    _______________________________________________________

Follow-up Comments:


-------------------------------------------------------
Date: Wed 31 Jul 2024 10:36:58 AM UTC By: Georg-Johann Lay <gjlayde>
In the code for ATtiny2313 below, the content of the XH register should be
ignored (masked out) when X is used to access RAM (or more generally, data in
the RAM address space, which extends from address 0 to 223).

However, XH is not ignored so that the code below runs into my_abort:


;;; avr-gcc foo.sx -o foo.elf -mmcu=attiny2313
;;; simulavr -d attiny2313 -f foo.elf -a 0x20 -e 0x21 -M

.data
var:
    .byte 123
.global __do_copy_data

.text
.global main
main:
    ldi XL, lo8(var)
    ;; Write garbage to XH which is in order for ATtiny2313:
    ;; That device has RAM_size = 128 and IO_space = 64,
    ;; which makes a valid RAM address range of 0...223, and hence a
    ;; core->dataAddressMask of 0xff.  This means that when simulavr is
masking the
    ;; address in X for access, the XH part will be masked out entirely.
    ;; On the instruction level this means that it is sufficient to
    ;; specify the lo8 part of an address for indirect RAM accesses.
    ldi XH, 1
    ld  r16, X
    cpi r16, 123
    brne my_abort
my_exit:
    out 0x1, r0
my_abort:
    out 0x0, r0
    ret









    _______________________________________________________
File Attachments:


-------------------------------------------------------
Name: foo.sx  Size: 786B
<https://file.savannah.nongnu.org/file/foo.sx?file_id=56330>

    AGPL NOTICE

These attachments are served by Savane. You can download the corresponding
source code of Savane at
https://git.savannah.nongnu.org/cgit/administration/savane.git/snapshot/savane-89cd07edc53b91897640ed1593bee414af194b8e.tar.gz

    _______________________________________________________

Reply to this item at:

  <https://savannah.nongnu.org/bugs/?66044>

_______________________________________________
Message sent via Savannah
https://savannah.nongnu.org/

Attachment: signature.asc
Description: PGP signature


reply via email to

[Prev in Thread] Current Thread [Next in Thread]