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| From: | David Smith |
| Subject: | Re: [Tinycc-devel] Transputer Target |
| Date: | Sun, 30 Jan 2022 10:53:18 +0000 |
| Thanks Jullien, The plan back in 2018 was to design a foc motor controller with co processors and peripherals directly attached to transputer links. I made a start developing a T80x compatible core mainly for the separate address and data bus. A great transputer resource The initial goal was to boot Helios or port ChibiOS. The transputer core was built using SpinalHDL with the hardware being a Lattice ECP5 fpga. I actually found SpinalHDL by accident whilst reading this Gameboy core series Charles (creator of SpinalHDL) won the riscv prize for his core https://github.com/SpinalHDL/VexRiscv I halted development of the transputer core and worked solely with Vex. I added a few custom instructions to Vex to assist foc algorithms. The instructions collected voltage, current and position sensor data that are directly attached to custom gpio CSR. Further CSR was used to send PWM back out to GaN drivers. The goal being a very low latency loop for high frequency motor torque control without SPI, buses and DMA in the loop. On 30 Jan 2022, at 06:03, Christian Jullien <eligis@orange.fr> wrote:
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