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sym to verilog-ams
From: |
karl |
Subject: |
sym to verilog-ams |
Date: |
Sun, 3 Apr 2022 13:14:57 +0200 (CEST) |
How do I conert a sym file to verilog ?
My conclusion is that it isn't meaningful to do automatic conversion
from sym file to verilog-ams file except perhaps for a first skeleton
containing the port names used.
And for a first skeleton, should a converter use the pinseq, pinnumber
or the pinlabel attribute for the ports ?
=====
Can one have mult. identical modules or must a converter output
just one ?
If there is a verilog-ams file for every sym file used, and if
they are `include-d in the verilog-ams version of a sch file,
then maybe we should do something like what is common for c-header
files:
`ifndef __SYM_xxx__
`define __SYM_xxx__ 1
... module definition ...
`endif
because in a hier. it could be included from different places.
=====
In lepton/geda, one can have different symbols for different parts of a
part (e.g. an ic). So one have to merge all symbols with the same final
refdes.
=====
This is testpt-1.sym as delivered with lepton.
///
v 20210407 2
P 100 0 100 200 1 0 0
{
T 300 0 5 10 0 0 0 0 1
pinseq=1
T 300 200 5 10 0 0 0 0 1
pinnumber=1
T 100 0 5 10 0 1 0 0 1
pintype=io
T 100 0 5 10 0 1 0 0 1
pinlabel=1
}
L 0 300 100 200 3 0 0 0 -1 -1
L 100 200 200 300 3 0 0 0 -1 -1
L 0 300 100 400 3 0 0 0 -1 -1
L 100 400 200 300 3 0 0 0 -1 -1
T 100 400 8 10 1 1 0 0 1
refdes=TP?
T 400 900 8 10 0 0 0 0 1
device=TESTPOINT
T 400 700 8 10 0 0 0 0 1
footprint=none
T 400 1100 8 10 0 0 0 0 1
numslots=0
T 400 500 8 10 0 0 0 0 1
symversion=0.1
///
The only thing of interest might be
. device attribute
. pin endpoint (100 200)
. pinnumber or -label
. pintype
. the filename
It might be translated into
module testpt (a);
inout a;
electrical a;
endmodule
module name might be file name sans .sym or the device attribute or
something else.
The pin name might come from pinnumber, pinseq, or the pinlabel
atrribute, or something else.
A testpoint is some kind of connector. How is connectors described in
verilog-ams ?
The pintype attribute [1] does not line up with the verilog ones.
According to [2], [3] is the only user of this and it checks which
connections are allowed.
[1] http://wiki.geda-project.org/geda:master_attributes_list#pintype
[2] https://archives.seul.org/geda/user/Sep-2010/msg00653.html
[3]
https://github.com/lepton-eda/lepton-eda/blob/master/utils/netlist/scheme/backend/gnet-drc2.scm
Regards,
/Karl Hammar
- sym to verilog-ams,
karl <=
- Re: sym to verilog-ams, Felix Salfelder, 2022/04/03
- Re: sym to verilog-ams, karl, 2022/04/04
- gnucap-geda, sym file hndling (was Re: sym to verilog-ams), karl, 2022/04/04
- Re: sym to verilog-ams, karl, 2022/04/05
- Re: sym to verilog-ams, al davis, 2022/04/06
- Re: sym to verilog-ams, karl, 2022/04/14