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Re: sym to verilog-ams
From: |
karl |
Subject: |
Re: sym to verilog-ams |
Date: |
Thu, 14 Apr 2022 15:31:12 +0200 (CEST) |
Al Davis:
...
> It's all about the circuit. The drawing is just a way to present the
> circuit
...
I have thought a while about this. I'd like to qoute
John Linsley Hood, The art of linear electronics
2:nd edition, p. 1
Basic design philosophy
The purpose of a circuit drawing is to give a rapid visual explanation
to the viewer of how the circuit works, and how the individual
component parts relate to one another.
Unfortunately, in pratice, darwings are often made with the sole aims
of showing the connections between the components in an accurate
manner and of producing a neat looking final result.
Wheter of not the actual interconnections are easy to follow, or how
readily the engineer can discover the way the circuit operates, may
not be a paricularly high priority at the time the drawing is made.
I view the schematic as documentaion, it is something more than
just a preprocessor to the pcb layout program.
Documentation comes in many forms, and we should be prepared for it to
be in a multiple of files, describing different parts and/or views of
the complete system, in differnt file formats and even prose.
In view of that I think that we should strive for is tools that helps us
keep the different files in check, to keep them consistent.
So, I consider theese questions more fruitful than doing the round
trip conversion:
. what kind of information is "duplicated" in the different formats
(in this case the sch/sym and verilog-ams files, and possible qucs)
. how do we check that that information is the same
. how do we notify the "other" format that the "first" one is changed
///
To do the round trip conversions, we need a file format that is
sufficiently rich to be able to describe both the in- and the outfile.
E.g.
. hierarchical design is easy in lepton/geda but is more or less
useless and awkward in kicad.
. in lepton/geda you can split a symbol in different parts so you can
describe e.g. the signal path for a rs232 connection from mcu to
a connector, you can't do that in kicad.
. lepton/geda file format is well described, kicad schematic format doc.
is lacking, but lepton/geda attributes are very loosly defined and I
guess kicad has better standardisation.
My guess is that differet schematic file formats is build upon different
consepts, how do we merge thoose different consepts without creating a
PL/1 situation.
If you say that this is for lepton/geda, qucs and gnucap, then that may
be possible, we here can define a verilog-ams addition that would suit
us. But someone wants to include kicad, pads, etc.
I have done a sym to kicad symbol converter, but not a sch converter.
I was involved in kicad input/output to/from pcb-rnd we have seen that
(geda) pcb and kicad pcbnew have more or less incompatible consepts.
I'd say for layout conversion, pcb-rnd is the way to go, the programmer
there (Igor2) has shown keen interest in interoperability.
The same programmer is working on a schematic program and it might be
that there is enough action there to solve the sch-file conversion
problem, though not lossless but sufficiently good.
Regards,
/Karl Hammar
- sym to verilog-ams, karl, 2022/04/03
- Re: sym to verilog-ams, Felix Salfelder, 2022/04/03
- Re: sym to verilog-ams, karl, 2022/04/04
- gnucap-geda, sym file hndling (was Re: sym to verilog-ams), karl, 2022/04/04
- Re: sym to verilog-ams, karl, 2022/04/05
- Re: sym to verilog-ams, al davis, 2022/04/06
- Re: sym to verilog-ams,
karl <=
Re: sym to verilog-ams, al davis, 2022/04/04
Re: sym to verilog-ams, al davis, 2022/04/04
- Re: sym to verilog-ams, karl, 2022/04/05
- attributes, possible interface, Felix Salfelder, 2022/04/18
- Re: attributes, possible interface, al davis, 2022/04/18
- Re: attributes, possible interface, Felix Salfelder, 2022/04/19
- Re: attributes, possible interface, al davis, 2022/04/19
- Re: attributes, possible interface, Felix Salfelder, 2022/04/20