Include and change working directory in GNU make

[Matt "strager" G.]

Hello,

I am using cmake to generate a Makefile for my project.  However, I
would like a special Makefile to generate that Makefile using cmake if
it doesn't exist already.  Also, I would like to send any targets
(except for cmake's Makefile, of course) to cmake's Makefile.

Currently I have this, basically:

#
------------------------------------------------------------------------------
# Build directory for cmake files -- hidden so it doesn't clutter .
BUILD_DIR = .build
# cmake's Makefile
MAKEFILE = ${BUILD_DIR}/Makefile

.PHONY: all

all: mysubproject1

# Some targets to redirect
mysubproject1:
    make -C ${BUILD_DIR} $@

mysubproject2:
    make -C ${BUILD_DIR} $@

mysubproject3:
    make -C ${BUILD_DIR} $@

# Generate cmake's Makefile
# Note that cmake's Makefile knows when the CMakeLists.txt files
# change, and remakes itself accordingly, so I don't do it here myself
${MAKEFILE}:
    [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}
    [ -f ${MAKEFILE} ] || (cd ${BUILD_DIR} && cmake ${CMAKE_OPTS} ..)
#
------------------------------------------------------------------------------

I have been looking for a more elegant solution.  In particular, I
would like to be able to use /any/ of the rules in cmake's Makefile
and not have to enter them in my own Makefile (as in the three
subprojects).  I have looked into the 'include' command, but it
doesn't work as I want it to because it does not change the current
working directory for the included Makefile.  For example, cmake's
Makefile calls other Makefiles recursively for each subproject, and
these paths are relative (by default it calls: $(MAKE) -f CMakeFiles/
Makefile2 all).

TL;DR: I need to change the current working directory when including a
Makefile as if it were called recursively, with -C.  OR!  I need to
pass "unknown" targets to a different Makefile.

Thanks!