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[PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec
From: |
Alistair Francis |
Subject: |
[PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec |
Date: |
Fri, 8 Sep 2023 16:04:10 +1000 |
From: Tommy Wu <tommy.wu@sifive.com>
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b8e0d0cb4c..4a0f6a89be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1684,7 +1684,7 @@ static int rmw_iprio(target_ulong xlen,
static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
- bool virt;
+ bool virt, isel_reserved;
uint8_t *iprio;
int ret = -EINVAL;
target_ulong priv, isel, vgein;
@@ -1694,6 +1694,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno,
target_ulong *val,
/* Decode register details from CSR number */
virt = false;
+ isel_reserved = false;
switch (csrno) {
case CSR_MIREG:
iprio = env->miprio;
@@ -1738,11 +1739,13 @@ static int rmw_xireg(CPURISCVState *env, int csrno,
target_ulong *val,
riscv_cpu_mxl_bits(env)),
val, new_val, wr_mask);
}
+ } else {
+ isel_reserved = true;
}
done:
if (ret) {
- return (env->virt_enabled && virt) ?
+ return (env->virt_enabled && virt && !isel_reserved) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
--
2.41.0
- [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path, (continued)
- [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/08
- [PULL 35/65] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/08
- [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/08
- [PULL 37/65] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/08
- [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 42/65] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/08
- [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/08
- [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/08
- [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes, Alistair Francis, 2023/09/08
- [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec,
Alistair Francis <=
- [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64, Alistair Francis, 2023/09/08
- [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/09/08
- [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/09/08
- [PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[], Alistair Francis, 2023/09/08
- [PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08