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[PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update
From: |
Alistair Francis |
Subject: |
[PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled |
Date: |
Fri, 8 Sep 2023 16:04:24 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dae259e02..03e936348a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -162,18 +162,17 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
};
-static bool isa_ext_is_enabled(RISCVCPU *cpu,
- const struct isa_ext_data *edata)
+static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
{
- bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
+ bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
return *ext_enabled;
}
-static void isa_ext_update_enabled(RISCVCPU *cpu,
- const struct isa_ext_data *edata, bool en)
+static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
+ bool en)
{
- bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
+ bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
*ext_enabled = en;
}
@@ -1045,9 +1044,10 @@ static void
riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
/* Force disable extensions if priv spec version does not match */
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
+ if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
(env->priv_ver < isa_edata_arr[i].min_version)) {
- isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
+ isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
+ false);
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
@@ -2346,7 +2346,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
**isa_str,
int i;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
g_free(old);
old = new;
--
2.41.0
- Re: [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper, (continued)
- [PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[], Alistair Francis, 2023/09/08
- [PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Alistair Francis, 2023/09/08
- [PULL 53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array(), Alistair Francis, 2023/09/08
- [PULL 54/65] target/riscv/cpu.c: limit cfg->vext_spec log message, Alistair Francis, 2023/09/08
- [PULL 55/65] target/riscv: add 'max' CPU type, Alistair Francis, 2023/09/08
- [PULL 56/65] avocado, risc-v: add tuxboot tests for 'max' CPU, Alistair Francis, 2023/09/08
- [PULL 57/65] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/09/08
- [PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled,
Alistair Francis <=
- [PULL 59/65] target/riscv: make CPUCFG() macro public, Alistair Francis, 2023/09/08
- [PULL 60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Alistair Francis, 2023/09/08
- [PULL 61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Alistair Francis, 2023/09/08
- [PULL 62/65] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/09/08
- [PULL 63/65] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Alistair Francis, 2023/09/08
- [PULL 64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/09/08
- [PULL 65/65] target/riscv/cpu.c: consider user option with RVG, Alistair Francis, 2023/09/08
- Re: [PULL 00/65] riscv-to-apply queue, Michael Tokarev, 2023/09/08
- Re: [PULL 00/65] riscv-to-apply queue, Stefan Hajnoczi, 2023/09/08