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[PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit
From: |
Alistair Francis |
Subject: |
[PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren |
Date: |
Mon, 11 Sep 2023 16:42:58 +1000 |
From: Rob Bradford <rbradford@rivosinc.com>
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by modifying OpenSBI to write max value to these CSRs and upon
subsequent read the appropriate number of bits for number of PMUs is
enabled and the TM bit is zero in mcountinhibit.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ca95ae1527..661744e6d4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1833,8 +1833,11 @@ static RISCVException write_mcountinhibit(CPURISCVState
*env, int csrno,
{
int cidx;
PMUCTRState *counter;
+ RISCVCPU *cpu = env_archcpu(env);
- env->mcountinhibit = val;
+ /* WARL register - disable unavailable counters; TM bit is always 0 */
+ env->mcountinhibit =
+ val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR);
/* Check if any other counter is also monitoring cycles/instructions */
for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
@@ -1857,7 +1860,11 @@ static RISCVException read_mcounteren(CPURISCVState
*env, int csrno,
static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->mcounteren = val;
+ RISCVCPU *cpu = env_archcpu(env);
+
+ /* WARL register - disable unavailable counters */
+ env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM
|
+ COUNTEREN_IR);
return RISCV_EXCP_NONE;
}
--
2.41.0
- [PULL v2 17/45] target/riscv: Add Zvknh ISA extension support, (continued)
- [PULL v2 17/45] target/riscv: Add Zvknh ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 18/45] target/riscv: Add Zvksh ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 19/45] target/riscv: Add Zvkg ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 20/45] crypto: Create sm4_subword, Alistair Francis, 2023/09/11
- [PULL v2 21/45] crypto: Add SM4 constant parameter CK, Alistair Francis, 2023/09/11
- [PULL v2 27/45] hw/intc: Make rtc variable names consistent, Alistair Francis, 2023/09/11
- [PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled, Alistair Francis, 2023/09/11
- [PULL v2 22/45] target/riscv: Add Zvksed ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d, Alistair Francis, 2023/09/11
- [PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation, Alistair Francis, 2023/09/11
- [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren,
Alistair Francis <=
- [PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext, Alistair Francis, 2023/09/11
- [PULL v2 31/45] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/11
- [PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/11
- [PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/11
- [PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/11
- [PULL v2 30/45] target/riscv: check the in-kernel irqchip support, Alistair Francis, 2023/09/11
- [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/11
- [PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/11
- [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS, Alistair Francis, 2023/09/11
- [PULL v2 37/45] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/11