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[PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension
From: |
Alistair Francis |
Subject: |
[PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension |
Date: |
Mon, 11 Sep 2023 16:43:10 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 8 ++++----
target/riscv/cpu.c | 4 ++--
target/riscv/cpu_helper.c | 6 +++---
target/riscv/csr.c | 12 ++++++------
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 31a8d80990..3d6ffaabc7 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -745,12 +745,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
-#define MENVCFG_HADE (1ULL << 61)
+#define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
/* For RV32 */
-#define MENVCFGH_HADE BIT(29)
+#define MENVCFGH_ADUE BIT(29)
#define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31)
@@ -763,12 +763,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
-#define HENVCFG_HADE MENVCFG_HADE
+#define HENVCFG_ADUE MENVCFG_ADUE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */
-#define HENVCFGH_HADE MENVCFGH_HADE
+#define HENVCFGH_ADUE MENVCFGH_ADUE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fae1c92c5c..8071f05f15 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -886,9 +886,9 @@ static void riscv_cpu_reset_hold(Object *obj)
env->two_stage_lookup = false;
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
+ (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
- (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
+ (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9f611d89bb..3a02079290 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -861,11 +861,11 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
- bool hade = env->menvcfg & MENVCFG_HADE;
+ bool adue = env->menvcfg & MENVCFG_ADUE;
if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
- hade = hade && (env->henvcfg & HENVCFG_HADE);
+ adue = adue && (env->henvcfg & HENVCFG_ADUE);
}
int ptshift = (levels - 1) * ptidxbits;
@@ -1026,7 +1026,7 @@ restart:
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte && !is_debug) {
- if (!hade) {
+ if (!adue) {
return TRANSLATE_FAIL;
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 661744e6d4..63c3b0d9fc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1957,7 +1957,7 @@ static RISCVException write_menvcfg(CPURISCVState *env,
int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
- (cfg->ext_svadu ? MENVCFG_HADE : 0);
+ (cfg->ext_svadu ? MENVCFG_ADUE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1977,7 +1977,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env,
int csrno,
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
- (cfg->ext_svadu ? MENVCFG_HADE : 0);
+ (cfg->ext_svadu ? MENVCFG_ADUE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@ -2029,7 +2029,7 @@ static RISCVException read_henvcfg(CPURISCVState *env,
int csrno,
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
* henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/
- *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -2046,7 +2046,7 @@ static RISCVException write_henvcfg(CPURISCVState *env,
int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
- mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
+ mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -2064,7 +2064,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
return ret;
}
- *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+ *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
@@ -2073,7 +2073,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env,
int csrno,
target_ulong val)
{
uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
- HENVCFG_HADE);
+ HENVCFG_ADUE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.41.0
- [PULL v2 27/45] hw/intc: Make rtc variable names consistent, (continued)
- [PULL v2 27/45] hw/intc: Make rtc variable names consistent, Alistair Francis, 2023/09/11
- [PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled, Alistair Francis, 2023/09/11
- [PULL v2 22/45] target/riscv: Add Zvksed ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d, Alistair Francis, 2023/09/11
- [PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation, Alistair Francis, 2023/09/11
- [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren, Alistair Francis, 2023/09/11
- [PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext, Alistair Francis, 2023/09/11
- [PULL v2 31/45] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/11
- [PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/11
- [PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/11
- [PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension,
Alistair Francis <=
- [PULL v2 30/45] target/riscv: check the in-kernel irqchip support, Alistair Francis, 2023/09/11
- [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/11
- [PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/11
- [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS, Alistair Francis, 2023/09/11
- [PULL v2 37/45] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/11
- [PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/11