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[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX cha
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From: |
Alistair Francis |
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Subject: |
[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes |
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Date: |
Mon, 11 Sep 2023 16:43:18 +1000 |
From: Leon Schuermann <leons@opentitan.org>
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes work even on locked regions when the global rule-lock bypass is
enabled.
Signed-off-by: Leon Schuermann <leons@opentitan.org>
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9d8db493e6..5e60c26031 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
*/
static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
{
+ /* mseccfg.RLB is set */
+ if (MSECCFG_RLB_ISSET(env)) {
+ return 0;
+ }
if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
return 1;
--
2.41.0
- Re: [PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build, (continued)
[PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/11
[PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/11
[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/11
[PULL v2 42/45] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/11
[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes,
Alistair Francis <=
[PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified spec, Alistair Francis, 2023/09/11
[PULL v2 45/45] target/riscv: don't read CSR in riscv_csrrw_do64, Alistair Francis, 2023/09/11
Re: [PULL v2 00/45] riscv-to-apply queue, Stefan Hajnoczi, 2023/09/11
Re: [PULL v2 00/45] riscv-to-apply queue, Michael Tokarev, 2023/09/12