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[PATCH v4 12/21] i386: Expose module level in CPUID[0x1F]
From: |
Zhao Liu |
Subject: |
[PATCH v4 12/21] i386: Expose module level in CPUID[0x1F] |
Date: |
Thu, 14 Sep 2023 15:21:50 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
(Tested CPU topology in CPUID[0x1F] leaf with various die/cluster
configurations in "-smp".)
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
---
Changes since v3:
* New patch to expose module level in 0x1F.
* Add Tested-by tag from Yongwei.
---
target/i386/cpu.c | 12 +++++++++++-
target/i386/cpu.h | 2 ++
target/i386/kvm/kvm.c | 2 +-
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cef9a4606d89..f0ddb253b6b5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -276,6 +276,8 @@ static uint32_t num_cpus_by_topo_level(X86CPUTopoInfo
*topo_info,
return 1;
case CPU_TOPO_LEVEL_CORE:
return topo_info->threads_per_core;
+ case CPU_TOPO_LEVEL_MODULE:
+ return topo_info->threads_per_core * topo_info->cores_per_module;
case CPU_TOPO_LEVEL_DIE:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die;
@@ -296,6 +298,8 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo
*topo_info,
return 0;
case CPU_TOPO_LEVEL_CORE:
return apicid_core_offset(topo_info);
+ case CPU_TOPO_LEVEL_MODULE:
+ return apicid_module_offset(topo_info);
case CPU_TOPO_LEVEL_DIE:
return apicid_die_offset(topo_info);
case CPU_TOPO_LEVEL_PACKAGE:
@@ -315,6 +319,8 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel
topo_level)
return CPUID_1F_ECX_TOPO_LEVEL_SMT;
case CPU_TOPO_LEVEL_CORE:
return CPUID_1F_ECX_TOPO_LEVEL_CORE;
+ case CPU_TOPO_LEVEL_MODULE:
+ return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
case CPU_TOPO_LEVEL_DIE:
return CPUID_1F_ECX_TOPO_LEVEL_DIE;
default:
@@ -346,6 +352,10 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t
count,
if (env->nr_dies > 1) {
set_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
}
+
+ if (env->nr_modules > 1) {
+ set_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap);
+ }
}
*ecx = count & 0xff;
@@ -6390,7 +6400,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
case 0x1F:
/* V2 Extended Topology Enumeration Leaf */
- if (topo_info.dies_per_pkg < 2) {
+ if (topo_info.modules_per_die < 2 && topo_info.dies_per_pkg < 2) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 556e80f29764..54019e82fdb4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1018,6 +1018,7 @@ enum CPUTopoLevel {
CPU_TOPO_LEVEL_INVALID,
CPU_TOPO_LEVEL_SMT,
CPU_TOPO_LEVEL_CORE,
+ CPU_TOPO_LEVEL_MODULE,
CPU_TOPO_LEVEL_DIE,
CPU_TOPO_LEVEL_PACKAGE,
CPU_TOPO_LEVEL_MAX,
@@ -1032,6 +1033,7 @@ enum CPUTopoLevel {
#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID
#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT
#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE
+#define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3
#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5
/* MSR Feature Bits */
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index e5cd7cc80616..545b2d46221e 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -1959,7 +1959,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
break;
}
case 0x1f:
- if (env->nr_dies < 2) {
+ if (env->nr_modules < 2 && env->nr_dies < 2) {
break;
}
/* fallthrough */
--
2.34.1
- Re: [PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies, (continued)
- [PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2023/09/14
- [PATCH v4 07/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/09/14
- [PATCH v4 08/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2023/09/14
- [PATCH v4 06/21] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4], Zhao Liu, 2023/09/14
- [PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/09/14
- [PATCH v4 11/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/09/14
- [PATCH v4 09/21] i386: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2023/09/14
- [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F],
Zhao Liu <=
- [PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/09/14
- [PATCH v4 16/21] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/09/14
- [PATCH v4 14/21] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/09/14
- [PATCH v4 15/21] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/09/14
- [PATCH v4 17/21] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/09/14
- [PATCH v4 18/21] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/09/14
- [PATCH v4 19/21] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/09/14
- [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/09/14