Re: [PATCH v3 2/4] hw/cxl: Use switch statements for read and write of cachemem registers

[Jonathan Cameron]

On Wed, 20 Sep 2023 08:08:39 +0300
Michael Tokarev <mjt@tls.msk.ru> wrote:

> 19.09.2023 12:34, Jonathan Cameron via wrote:
> > Establishing that only register accesses of size 4 and 8 can occur
> > using these functions requires looking at their callers. Make it
> > easier to see that by using switch statements.
> > Assertions are used to enforce that the register storage is of the
> > matching size, allowing fixed values to be used for divisors of
> > the array indices.
> > 
> > Suggested-by: Michael Tokarev <mjt@tls.msk.ru>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Reviewed-by: Fan Ni <fan.ni@samsung.com>  
> 
> > @@ -117,25 +125,36 @@ static void cxl_cache_mem_write_reg(void *opaque, 
> > hwaddr offset, uint64_t value,
> >       ComponentRegisters *cregs = &cxl_cstate->crb;
> >       uint32_t mask;  
> ..
> This hunk does not apply to qemu/master.  Is it based on some other
> change missing in this area?
> 
> I thought about collecting all this and pushing trivial-patches but
> stumbled upon this one.

See the dependencies listed in the cover letter for this set.
The HDM decoder series in particular affects the same code.

There are several series that are more urgent than this one as I'm keen
to get some features upstream as well as cleanup this cycle.
I could reorder the tree, but that would have knock on impacts on those
series. Hopefully nothing that would require re-review, but still noisy.

Thanks for considering / trying these though and for picking up
the ones that were dependency free.

Jonathan


> 
> Thanks,
> 
> /mjt
>