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[PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/w
From: |
Jonathan Cameron |
Subject: |
[PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions |
Date: |
Mon, 25 Sep 2023 17:11:22 +0100 |
From: Gregory Price <gourry.memverge@gmail.com>
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/mem/cxl_type3.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index cc8220592f..a766c64575 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -888,17 +888,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d,
MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
+ CXLType3Dev *ct3d = CXL_TYPE3(d);
uint64_t dpa_offset = 0;
AddressSpace *as = NULL;
int res;
- res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
+ res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
&as, &dpa_offset);
if (res) {
return MEMTX_ERROR;
}
- if (sanitize_running(&CXL_TYPE3(d)->cci)) {
+ if (sanitize_running(&ct3d->cci)) {
qemu_guest_getrandom_nofail(data, size);
return MEMTX_OK;
}
@@ -909,17 +910,18 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr
host_addr, uint64_t *data,
MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
unsigned size, MemTxAttrs attrs)
{
+ CXLType3Dev *ct3d = CXL_TYPE3(d);
uint64_t dpa_offset = 0;
AddressSpace *as = NULL;
int res;
- res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
+ res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
&as, &dpa_offset);
if (res) {
return MEMTX_ERROR;
}
- if (sanitize_running(&CXL_TYPE3(d)->cci)) {
+ if (sanitize_running(&ct3d->cci)) {
return MEMTX_OK;
}
--
2.39.2
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, (continued)
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, Jonathan Cameron, 2023/09/25
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed, Jonathan Cameron, 2023/09/25
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25
- [PATCH 14/19] hw/cxl/mbox: Add support for background operations, Jonathan Cameron, 2023/09/25
- [PATCH 15/19] hw/cxl/mbox: Wire up interrupts for background completion, Jonathan Cameron, 2023/09/25
- [PATCH 16/19] hw/cxl: Add support for device sanitation, Jonathan Cameron, 2023/09/25
- [PATCH 17/19] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions,
Jonathan Cameron <=
- [PATCH 18/19] hw/cxl: Add dummy security state get, Jonathan Cameron, 2023/09/25
- [PATCH 19/19] hw/cxl: Add tunneled command support to mailbox for switch cci/mctp., Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25
- Re: [PATCH 00/19] QEMU: CXL mailbox rework and features, Gregory Price, 2023/09/28