[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 1/5] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
From: |
Peter Maydell |
Subject: |
[PULL 1/5] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 |
Date: |
Tue, 2 Apr 2024 11:29:47 +0100 |
The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and
EL0 accesses to cp15 registers. We incorrectly implemented this so
they trap to EL1 when we detect the need for a HSTR trap at code
generation time. (The check in access_check_cp_reg() which we do at
runtime to catch traps from EL0 is correctly routing them to EL2.)
Use the correct target EL when generating the code to take the trap.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226
Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over
UNDEF-at-EL1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org
---
target/arm/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index c8a24706750..69585e6003d 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -4585,7 +4585,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
tcg_gen_andi_i32(t, t, 1u << maskbit);
tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
- gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
/*
* gen_exception_insn() will set is_jmp to DISAS_NORETURN,
* but since we're conditionally branching over it, we want
--
2.34.1
- [PULL 0/5] target-arm queue, Peter Maydell, 2024/04/02
- [PULL 3/5] hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled, Peter Maydell, 2024/04/02
- [PULL 5/5] raspi4b: Reduce RAM to 1Gb on 32-bit hosts, Peter Maydell, 2024/04/02
- [PULL 2/5] docs: sbsa: update specs, add dt note, Peter Maydell, 2024/04/02
- [PULL 1/5] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1,
Peter Maydell <=
- [PULL 4/5] tests/qtest: Fix STM32L4x5 GPIO test on 32-bit, Peter Maydell, 2024/04/02
- Re: [PULL 0/5] target-arm queue, Peter Maydell, 2024/04/02