[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 19/45] target/hppa: Rename cond_make_* helpers
From: |
Richard Henderson |
Subject: |
[PATCH 19/45] target/hppa: Rename cond_make_* helpers |
Date: |
Wed, 24 Apr 2024 16:59:57 -0700 |
Use 'v' for a variable that needs copying, 't' for a temp that
doesn't need copying, and 'i' for an immediate, and use this
naming for both arguments of the comparison. So:
cond_make_tmp -> cond_make_tt
cond_make_0_tmp -> cond_make_ti
cond_make_0 -> cond_make_vi
cond_make -> cond_make_vv
Pass 0 explictly, rather than implicitly in the function name.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 52 ++++++++++++++++++++---------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index dd3921dbf9..a1132c884f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -344,32 +344,32 @@ static DisasCond cond_make_n(void)
};
}
-static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
+static DisasCond cond_make_tt(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
{
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 };
}
-static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0)
+static DisasCond cond_make_ti(TCGCond c, TCGv_i64 a0, uint64_t imm)
{
- return cond_make_tmp(c, a0, tcg_constant_i64(0));
+ return cond_make_tt(c, a0, tcg_constant_i64(imm));
}
-static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0)
+static DisasCond cond_make_vi(TCGCond c, TCGv_i64 a0, uint64_t imm)
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, a0);
- return cond_make_0_tmp(c, tmp);
+ return cond_make_ti(c, tmp, imm);
}
-static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
+static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_mov_i64(t0, a0);
tcg_gen_mov_i64(t1, a1);
- return cond_make_tmp(c, t0, t1);
+ return cond_make_tt(c, t0, t1);
}
static void cond_free(DisasCond *cond)
@@ -787,7 +787,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf,
bool d,
tcg_gen_ext32u_i64(tmp, res);
res = tmp;
}
- cond = cond_make_0(TCG_COND_EQ, res);
+ cond = cond_make_vi(TCG_COND_EQ, res, 0);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new_i64();
@@ -795,7 +795,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf,
bool d,
if (!d) {
tcg_gen_ext32s_i64(tmp, tmp);
}
- cond = cond_make_0_tmp(TCG_COND_LT, tmp);
+ cond = cond_make_ti(TCG_COND_LT, tmp, 0);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
/*
@@ -817,10 +817,10 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf,
bool d,
tcg_gen_sari_i64(tmp, tmp, 63);
tcg_gen_and_i64(tmp, tmp, res);
}
- cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
+ cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
break;
case 4: /* NUV / UV (!UV / UV) */
- cond = cond_make_0(TCG_COND_EQ, uv);
+ cond = cond_make_vi(TCG_COND_EQ, uv, 0);
break;
case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
tmp = tcg_temp_new_i64();
@@ -828,7 +828,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf,
bool d,
if (!d) {
tcg_gen_ext32u_i64(tmp, tmp);
}
- cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
+ cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
break;
case 6: /* SV / NSV (V / !V) */
if (!d) {
@@ -836,12 +836,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf,
bool d,
tcg_gen_ext32s_i64(tmp, sv);
sv = tmp;
}
- cond = cond_make_0(TCG_COND_LT, sv);
+ cond = cond_make_ti(TCG_COND_LT, sv, 0);
break;
case 7: /* OD / EV */
tmp = tcg_temp_new_i64();
tcg_gen_andi_i64(tmp, res, 1);
- cond = cond_make_0_tmp(TCG_COND_NE, tmp);
+ cond = cond_make_ti(TCG_COND_NE, tmp, 0);
break;
default:
g_assert_not_reached();
@@ -903,9 +903,9 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned
cf, bool d,
tcg_gen_ext32s_i64(t1, in1);
tcg_gen_ext32s_i64(t2, in2);
}
- return cond_make_tmp(tc, t1, t2);
+ return cond_make_tt(tc, t1, t2);
}
- return cond_make(tc, in1, in2);
+ return cond_make_vv(tc, in1, in2);
}
/*
@@ -977,9 +977,9 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned
cf, bool d,
} else {
tcg_gen_ext32s_i64(tmp, res);
}
- return cond_make_0_tmp(tc, tmp);
+ return cond_make_ti(tc, tmp, 0);
}
- return cond_make_0(tc, res);
+ return cond_make_vi(tc, res, 0);
}
/* Similar, but for shift/extract/deposit conditions. */
@@ -1038,7 +1038,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d,
TCGv_i64 res)
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, sgns);
- return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp);
+ return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0);
}
static TCGv_i64 get_carry(DisasContext *ctx, bool d,
@@ -1452,7 +1452,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned
rt, TCGv_i64 in1,
}
tcg_gen_andi_i64(cb, cb, test_cb);
- cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb);
+ cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0);
}
if (is_tc) {
@@ -3541,7 +3541,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
tcg_gen_shl_i64(tmp, tcg_r, tmp);
}
- cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
+ cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3558,7 +3558,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
p = a->p | (a->d ? 0 : 32);
tcg_gen_shli_i64(tmp, tcg_r, p);
- cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
+ cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -4362,7 +4362,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
switch (a->c) {
case 0: /* simple */
tcg_gen_andi_i64(t, t, 0x4000000);
- ctx->null_cond = cond_make_0(TCG_COND_NE, t);
+ ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
goto done;
case 2: /* rej */
inv = true;
@@ -4392,16 +4392,16 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
if (inv) {
TCGv_i64 c = tcg_constant_i64(mask);
tcg_gen_or_i64(t, t, c);
- ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
+ ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c);
} else {
tcg_gen_andi_i64(t, t, mask);
- ctx->null_cond = cond_make_0(TCG_COND_EQ, t);
+ ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0);
}
} else {
unsigned cbit = (a->y ^ 1) - 1;
tcg_gen_extract_i64(t, t, 21 - cbit, 1);
- ctx->null_cond = cond_make_0(TCG_COND_NE, t);
+ ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0);
}
done:
--
2.34.1
- [PATCH 16/45] target/hppa: Always make a copy in do_ibranch_priv, (continued)
- [PATCH 16/45] target/hppa: Always make a copy in do_ibranch_priv, Richard Henderson, 2024/04/24
- [PATCH 18/45] target/hppa: Use displacements in DisasIAQE, Richard Henderson, 2024/04/24
- [PATCH 24/45] target/hppa: Use TCG_COND_TST* in trans_bb_imm, Richard Henderson, 2024/04/24
- [PATCH 27/45] target/hppa: Remove cond_free, Richard Henderson, 2024/04/24
- [PATCH 03/45] target/hppa: Move constant destination check into use_goto_tb, Richard Henderson, 2024/04/24
- [PATCH 05/45] target/hppa: Allow prior nullification in do_ibranch, Richard Henderson, 2024/04/24
- [PATCH 13/45] target/hppa: Add space arguments to install_iaq_entries, Richard Henderson, 2024/04/24
- [PATCH 10/45] target/hppa: Skip nullified insns in unconditional dbranch path, Richard Henderson, 2024/04/24
- [PATCH 15/45] target/hppa: Use umax in do_ibranch_priv, Richard Henderson, 2024/04/24
- [PATCH 20/45] target/hppa: Use TCG_COND_TST* in do_cond, Richard Henderson, 2024/04/24
- [PATCH 19/45] target/hppa: Rename cond_make_* helpers,
Richard Henderson <=
- [PATCH 04/45] target/hppa: Pass displacement to do_dbranch, Richard Henderson, 2024/04/24
- [PATCH 14/45] target/hppa: Add space argument to do_ibranch, Richard Henderson, 2024/04/24
- [PATCH 12/45] target/hppa: Add IASQ entries to DisasContext, Richard Henderson, 2024/04/24
- [PATCH 22/45] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond, Richard Henderson, 2024/04/24
- [PATCH 23/45] target/hppa: Use TCG_COND_TST* in do_unit_addsub, Richard Henderson, 2024/04/24
- [PATCH 29/45] target/hppa: Use delay_excp for conditional traps, Richard Henderson, 2024/04/24
- [PATCH 28/45] target/hppa: Introduce DisasDelayException, Richard Henderson, 2024/04/24
- [PATCH 07/45] target/hppa: Add install_iaq_entries, Richard Henderson, 2024/04/24
- [PATCH 17/45] target/hppa: Introduce and use DisasIAQE for branch management, Richard Henderson, 2024/04/24
- [PATCH 11/45] target/hppa: Simplify TB end, Richard Henderson, 2024/04/24