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[PATCH 07/45] target/hppa: Add install_iaq_entries
From: |
Richard Henderson |
Subject: |
[PATCH 07/45] target/hppa: Add install_iaq_entries |
Date: |
Wed, 24 Apr 2024 16:59:45 -0700 |
Instead of two separate cpu_iaoq_entry calls, use one call to update
both IAQ_Front and IAQ_Back. Simplify with an argument combination
that automatically handles a simple increment from Front to Back.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 64 +++++++++++++++++++++--------------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index dfdcb3e23c..cad33e7aa6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -616,6 +616,23 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64
dest,
}
}
+static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv,
+ uint64_t ni, TCGv_i64 nv)
+{
+ copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv);
+
+ /* Allow ni variable, with nv null, to indicate a trivial advance. */
+ if (ni != -1 || nv) {
+ copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv);
+ } else if (bi != -1) {
+ copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL);
+ } else {
+ tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4);
+ tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b,
+ gva_offset_mask(ctx->tb_flags));
+ }
+}
+
static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp)
{
return ctx->iaoq_f + disp + 8;
@@ -628,8 +645,7 @@ static void gen_excp_1(int exception)
static void gen_excp(DisasContext *ctx, int exception)
{
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
gen_excp_1(exception);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -683,12 +699,10 @@ static void gen_goto_tb(DisasContext *ctx, int which,
{
if (use_goto_tb(ctx, b, n)) {
tcg_gen_goto_tb(which);
- copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL);
- copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL);
+ install_iaq_entries(ctx, b, NULL, n, NULL);
tcg_gen_exit_tb(ctx->base.tb, which);
} else {
- copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b);
- copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var);
+ install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var);
tcg_gen_lookup_and_goto_ptr();
}
}
@@ -1882,9 +1896,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
}
if (is_n) {
if (use_nullify_skip(ctx)) {
- copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next);
- tcg_gen_addi_i64(next, next, 4);
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next);
+ install_iaq_entries(ctx, -1, next, -1, NULL);
nullify_set(ctx, 0);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
return true;
@@ -1899,14 +1911,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
nullify_over(ctx);
if (is_n && use_nullify_skip(ctx)) {
- copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest);
- next = tcg_temp_new_i64();
- tcg_gen_addi_i64(next, dest, 4);
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next);
+ install_iaq_entries(ctx, -1, dest, -1, NULL);
nullify_set(ctx, 0);
} else {
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest);
+ install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest);
nullify_set(ctx, is_n);
}
if (link != 0) {
@@ -1997,9 +2005,7 @@ static void do_page_zero(DisasContext *ctx)
tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
tmp = tcg_temp_new_i64();
tcg_gen_ori_i64(tmp, cpu_gr[31], 3);
- copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp);
- tcg_gen_addi_i64(tmp, tmp, 4);
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp);
+ install_iaq_entries(ctx, -1, tmp, -1, NULL);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
break;
@@ -2743,8 +2749,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
nullify_over(ctx);
/* Advance the instruction queue. */
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
- copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b,
+ ctx->iaoq_n, ctx->iaoq_n_var);
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
@@ -3897,18 +3903,15 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b);
}
if (a->n && use_nullify_skip(ctx)) {
- copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp);
- tcg_gen_addi_i64(tmp, tmp, 4);
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp);
+ install_iaq_entries(ctx, -1, tmp, -1, NULL);
tcg_gen_mov_i64(cpu_iasq_f, new_spc);
tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f);
nullify_set(ctx, 0);
} else {
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp);
tcg_gen_mov_i64(cpu_iasq_b, new_spc);
nullify_set(ctx, a->n);
}
@@ -4017,11 +4020,10 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a)
nullify_over(ctx);
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);
+ install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest);
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
- copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest);
tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest));
if (a->l) {
copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var);
@@ -4720,8 +4722,8 @@ static void hppa_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
if (ctx->iaoq_f == -1) {
- copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b);
- copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
+ install_iaq_entries(ctx, -1, cpu_iaoq_b,
+ ctx->iaoq_n, ctx->iaoq_n_var);
#ifndef CONFIG_USER_ONLY
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
#endif
@@ -4750,8 +4752,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
case DISAS_TOO_MANY:
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
- copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f);
- copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b);
+ install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f,
+ ctx->iaoq_b, cpu_iaoq_b);
nullify_save(ctx);
/* FALLTHRU */
case DISAS_IAQ_N_UPDATED:
--
2.34.1
- [PATCH 15/45] target/hppa: Use umax in do_ibranch_priv, (continued)
- [PATCH 15/45] target/hppa: Use umax in do_ibranch_priv, Richard Henderson, 2024/04/24
- [PATCH 20/45] target/hppa: Use TCG_COND_TST* in do_cond, Richard Henderson, 2024/04/24
- [PATCH 19/45] target/hppa: Rename cond_make_* helpers, Richard Henderson, 2024/04/24
- [PATCH 04/45] target/hppa: Pass displacement to do_dbranch, Richard Henderson, 2024/04/24
- [PATCH 14/45] target/hppa: Add space argument to do_ibranch, Richard Henderson, 2024/04/24
- [PATCH 12/45] target/hppa: Add IASQ entries to DisasContext, Richard Henderson, 2024/04/24
- [PATCH 22/45] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond, Richard Henderson, 2024/04/24
- [PATCH 23/45] target/hppa: Use TCG_COND_TST* in do_unit_addsub, Richard Henderson, 2024/04/24
- [PATCH 29/45] target/hppa: Use delay_excp for conditional traps, Richard Henderson, 2024/04/24
- [PATCH 28/45] target/hppa: Introduce DisasDelayException, Richard Henderson, 2024/04/24
- [PATCH 07/45] target/hppa: Add install_iaq_entries,
Richard Henderson <=
- [PATCH 17/45] target/hppa: Introduce and use DisasIAQE for branch management, Richard Henderson, 2024/04/24
- [PATCH 11/45] target/hppa: Simplify TB end, Richard Henderson, 2024/04/24
- [PATCH 09/45] target/hppa: Delay computation of IAQ_Next, Richard Henderson, 2024/04/24
- [PATCH 25/45] target/hppa: Use registerfields.h for FPSR, Richard Henderson, 2024/04/24
- [PATCH 32/45] target/hppa: Store full iaoq_f and page bits of iaoq_d in TB, Richard Henderson, 2024/04/24
- [PATCH 31/45] linux-user/hppa: Force all code addresses to PRIV_USER, Richard Henderson, 2024/04/24
- [PATCH 26/45] target/hppa: Use TCG_COND_TST* in trans_ftest, Richard Henderson, 2024/04/24
- [PATCH 30/45] target/hppa: Use delay_excp for conditional trap on overflow, Richard Henderson, 2024/04/24
- [PATCH 34/45] target/hppa: Improve hppa_cpu_dump_state, Richard Henderson, 2024/04/24
- [PATCH 36/45] target/hppa: Manage PSW_X and PSW_B in translator, Richard Henderson, 2024/04/24