[PATCH v2 1/6] hw/ppc: remove SPI responder model

qemu-ppc

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[PATCH v2 1/6] hw/ppc: remove SPI responder model

From:	Chalapathi V
Subject:	[PATCH v2 1/6] hw/ppc: remove SPI responder model
Date:	Tue, 9 Apr 2024 12:56:55 -0500

-- Empty commit to align the patch numbers between PATCH v1 and PATCH v2.
SPI responder model is removed as pnv spi controller and seeprom is
implemented using QEMU SSI framework.

Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>

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[PATCH v2 0/6] hw/ppc: SPI model, Chalapathi V, 2024/04/09
- [PATCH v2 1/6] hw/ppc: remove SPI responder model, Chalapathi V <=
  - Re: [PATCH v2 1/6] hw/ppc: remove SPI responder model, Cédric Le Goater, 2024/04/15
- [PATCH v2 3/6] hw/ppc: SPI controller model - sequencer and shifter, Chalapathi V, 2024/04/09
  - Re: [PATCH v2 3/6] hw/ppc: SPI controller model - sequencer and shifter, Cédric Le Goater, 2024/04/16
    - Re: [PATCH v2 3/6] hw/ppc: SPI controller model - sequencer and shifter, Chalapathi V, 2024/04/16
- [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation, Chalapathi V, 2024/04/09
  - Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation, Cédric Le Goater, 2024/04/15
    - Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation, Chalapathi V, 2024/04/16
    - Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation, Cédric Le Goater, 2024/04/22
- [PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM model, Chalapathi V, 2024/04/09
  - Re: [PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM model, Cédric Le Goater, 2024/04/22

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