connecting narrow bus to a wide one

[Tuukka Toivonen]

I'm unable to connect narrow busses into wide busses using the Wire Con
-component in schematics technology. It connects, yes, but when i try to
simulate the VHDL compiler complains: the generated VHDL seems to be
illegal (altought I'm not sure, I don't really know VHDL).

Am I doing something wrong or is this a bug to be fixed?

This VHDL is generated:

-- VHDL automatically generated from facet compo{sch}
entity compo is port(in_0_, in_1_, in_2_, in_3_: in BIT; out_0_,
 out_1_, out_2_, out_3_: out BIT);
  end compo;
architecture compo_BODY of compo is
  component subcompo port(X_0_, X_1_: in BIT; Y_0_, Y_1_: out BIT);
    end component;
  signal in_2_, in_3_, out_0_, out_1_, out_2_, out_3_, in_0_, in_1_:
 BIT;
begin
  node7: subcompo port map(in_2_, in_3_, out_2_, out_3_);
  node8: subcompo port map(in_0_, in_1_, out_0_, out_1_);
end compo_BODY;

And the compiler complains:

Converting layout in facet compo{sch}, writing VHDL to facet compo{vhdl}
ERROR on line 8, Signal previously defined:
signal in_0_, in_1_, out_2_, out_3_, out_0_, out_1_, in_2_, in_3_: 
       ^

See also
http://www.ee.oulu.fi/~tuukkat/electric/bug-busbus.txt
which is the schematics causing problems and
http://www.ee.oulu.fi/~tuukkat/electric/bug-busbus.desc