Re: [Qemu-devel] [PATCH v2 5/9] target/mips: Extend gen_scwp() functionality to support EVA

[Aleksandar Rikalo]

> From: Aleksandar Markovic <address@hidden>
> Sent: Wednesday, January 23, 2019 12:15 PM
> To: address@hidden
> Cc: address@hidden; Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH v2 5/9] target/mips: Extend gen_scwp() functionality to 
> support EVA
>
> From: Aleksandar Markovic <address@hidden>
>
> Extend gen_scwp() functionality to support EVA by adding an
> additional argument, modify internals of the function to handle
> new functionality, and accordingly change its invocations.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
>  target/mips/translate.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>

gen_scwp() and gen_sc() should be consistent (with this patch, they both 
support EVA, but their parameters are organized differently). But, since this 
inconsistency does not effect the end result, and if you intend to do a similar 
change to gen_sc(), I support this patch:

Reviewed-by: Aleksandar Rikalo <address@hidden>


> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index b362b03..aaf7dff 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t 
> opc, int rt,
>  }
>
>  static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
> -                    uint32_t reg1, uint32_t reg2)
> +                    uint32_t reg1, uint32_t reg2, bool eva)
>  {
>      TCGv taddr = tcg_temp_local_new();
>      TCGv lladdr = tcg_temp_local_new();
> @@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, 
> int16_t offset,
>
>      tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
>      tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
> -                               ctx->mem_idx, MO_64);
> +                               eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
>      if (reg1 != 0) {
>          tcg_gen_movi_tl(cpu_gpr[reg1], 1);
>      }
> @@ -21550,7 +21550,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState 
> *env, DisasContext *ctx)
>                          break;
>                      case NM_SCWP:
>                          check_xnp(ctx);
> -                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5));
> +                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5),
> +                                 false);
>                          break;
>                      }
>                      break;
> @@ -21654,7 +21655,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState 
> *env, DisasContext *ctx)
>                          check_xnp(ctx);
>                          check_eva(ctx);
>                          check_cp0_enabled(ctx);
> -                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5));
> +                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5),
> +                                 true);
>                          break;
>                      default:
>                          generate_exception_end(ctx, EXCP_RI);
> --
> 2.7.4
>