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[Qemu-devel] [PULL 02/22] target/arm: Add PSTATE.BTYPE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/22] target/arm: Add PSTATE.BTYPE |
Date: |
Tue, 5 Feb 2019 17:04:50 +0000 |
From: Richard Henderson <address@hidden>
Place this in its own field within ENV, as that will
make it easier to reset from within TCG generated code.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 8 ++++++--
target/arm/translate-a64.c | 3 +++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0c7ea39f1ae..58f99985c24 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -234,6 +234,7 @@ typedef struct CPUARMState {
* semantics as for AArch32, as described in the comments on each field)
* nRW (also known as M[4]) is kept, inverted, in env->aarch64
* DAIF (exception masks) are kept in env->daif
+ * BTYPE is kept in env->btype
* all other bits are stored in their correct places in env->pstate
*/
uint32_t pstate;
@@ -263,6 +264,7 @@ typedef struct CPUARMState {
uint32_t GE; /* cpsr[19:16] */
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
+ uint32_t btype; /* BTI branch type. spsr[11:10]. */
uint64_t daif; /* exception masks, in the bits they are in PSTATE */
uint64_t elr_el[4]; /* AArch64 exception link regs */
@@ -1206,6 +1208,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_I (1U << 7)
#define PSTATE_A (1U << 8)
#define PSTATE_D (1U << 9)
+#define PSTATE_BTYPE (3U << 10)
#define PSTATE_IL (1U << 20)
#define PSTATE_SS (1U << 21)
#define PSTATE_V (1U << 28)
@@ -1214,7 +1217,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_N (1U << 31)
#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
-#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
+#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
/* Mode values for AArch64 */
#define PSTATE_MODE_EL3h 13
#define PSTATE_MODE_EL3t 12
@@ -1246,7 +1249,7 @@ static inline uint32_t pstate_read(CPUARMState *env)
ZF = (env->ZF == 0);
return (env->NF & 0x80000000) | (ZF << 30)
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
- | env->pstate | env->daif;
+ | env->pstate | env->daif | (env->btype << 10);
}
static inline void pstate_write(CPUARMState *env, uint32_t val)
@@ -1256,6 +1259,7 @@ static inline void pstate_write(CPUARMState *env,
uint32_t val)
env->CF = (val >> 29) & 1;
env->VF = (val << 3) & 0x80000000;
env->daif = val & PSTATE_DAIF;
+ env->btype = (val >> 10) & 3;
env->pstate = val & ~CACHED_PSTATE_BITS;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a1997e3ae28..0b94d9455b7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -163,6 +163,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
el,
psr & PSTATE_SP ? 'h' : 't');
+ if (cpu_isar_feature(aa64_bti, cpu)) {
+ cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
+ }
if (!(flags & CPU_DUMP_FPU)) {
cpu_fprintf(f, "\n");
return;
--
2.20.1
- [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 02/22] target/arm: Add PSTATE.BTYPE,
Peter Maydell <=
- [Qemu-devel] [PULL 10/22] linux-user: Implement PR_PAC_RESET_KEYS, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 21/22] hw/arm/boot: Support DTB autoload for firmware-only boots, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 01/22] target/arm: Introduce isar_feature_aa64_bti, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 15/22] target/arm: Enable TBI for user-only, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 04/22] exec: Add target-specific tlb bits to MemTxAttrs, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 07/22] target/arm: Reset btype for direct branches, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 09/22] target/arm: Enable BTI for -cpu max, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 12/22] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore, Peter Maydell, 2019/02/05