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Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
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Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 10:41:04 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
e2a93498c7 target/riscv: Remaining rvc insn reuse 32 bit translators
3f59fb9099 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
c3ad74f61a target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
b9d6ccca81 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
07776db255 target/riscv: Convert @cs_2 insns to share translation functions
bbeb07d1c1 target/riscv: Remove decode_RV32_64G()
8c8e0054b7 target/riscv: Remove gen_system()
e878cb4757 target/riscv: Rename trans_arith to gen_arith
e9bf9ba1ef target/riscv: Remove manual decoding of RV32/64M insn
7d02316889 target/riscv: Remove shift and slt insn manual decoding
4779f009ef target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0becb12c06 target/riscv: Move gen_arith_imm() decoding into trans_* functions
6934b41240 target/riscv: Remove manual decoding from gen_store()
f40c582d09 target/riscv: Remove manual decoding from gen_load()
3257410d02 target/riscv: Remove manual decoding from gen_branch()
68963c7308 target/riscv: Remove gen_jalr()
351570bad7 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
dc7cacdecf target/riscv: Convert quadrant 1 of RVXC insns to decodetree
3c963274bc target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae87b5ebb4 target/riscv: Convert RV priv insns to decodetree
67b8d1c9ab target/riscv: Convert RV64D insns to decodetree
3dbfe2e6d2 target/riscv: Convert RV32D insns to decodetree
a6305e03b3 target/riscv: Convert RV64F insns to decodetree
93300752fd target/riscv: Convert RV32F insns to decodetree
ab18a012c2 target/riscv: Convert RV64A insns to decodetree
3a9341dd5f target/riscv: Convert RV32A insns to decodetree
4f8f8626aa target/riscv: Convert RVXM insns to decodetree
e97b251f74 target/riscv: Convert RVXI csr insns to decodetree
2e9fa3a07a target/riscv: Convert RVXI fence insns to decodetree
d63e9306d1 target/riscv: Convert RVXI arithmetic insns to decodetree
79cbd6c743 target/riscv: Convert RV64I load/store insns to decodetree
c3af671a8f target/riscv: Convert RV32I load/store insns to decodetree
ea9489de9b target/riscv: Convert RVXI branch insns to decodetree
ce8dc97c46 target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit ce8dc97c46f0 (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit ea9489de9be2 (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit c3af671a8f6f (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit 79cbd6c7434d (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit d63e9306d19a (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit 2e9fa3a07aca (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit e97b251f7436 (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit 4f8f8626aacc (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit 3a9341dd5f2f (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit ab18a012c2d8 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit 93300752fdaf (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit a6305e03b3cc (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit 3dbfe2e6d24b (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit 67b8d1c9ab86 (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit ae87b5ebb451 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit 3c963274bcda (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit dc7cacdecf57 (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit 351570bad75b (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit 68963c730858 (target/riscv: Remove gen_jalr())
20/34 Checking commit 3257410d028f (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit f40c582d0941 (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit 6934b412409c (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit 0becb12c0675 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit 4779f009ef4a (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit 7d0231688996 (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit e9bf9ba1efe6 (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit e878cb475771 (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit 8c8e0054b785 (target/riscv: Remove gen_system())
29/34 Checking commit bbeb07d1c14f (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit 07776db25587 (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit b9d6ccca8132 (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit c3ad74f61ad1 (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit 3f59fb90995b (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit e2a93498c7fd (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, (continued)
- [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree,
no-reply <=
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27