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[PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode
From: |
Song Gao |
Subject: |
[PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode |
Date: |
Tue, 22 Aug 2023 11:27:15 +0800 |
From: Jiajie Chen <c@jia.je>
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/translate.c | 8 ++++++++
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 689da19ed0..de7c1c5d1f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -236,6 +236,14 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base,
target_long ofs)
return make_address_x(ctx, base, addend);
}
+static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
+{
+ if (ctx->va32) {
+ addr = (int32_t)addr;
+ }
+ return addr;
+}
+
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc
b/target/loongarch/insn_trans/trans_arith.c.inc
index 43d6cf261d..2aea4e41d5 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -72,7 +72,7 @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a,
target_ulong (*func)(target_ulong, int))
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
- target_ulong addr = func(ctx->base.pc_next, a->imm);
+ target_ulong addr = make_address_pc(ctx, func(ctx->base.pc_next, a->imm));
tcg_gen_movi_tl(dest, addr);
gen_set_gpr(a->rd, dest, EXT_NONE);
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc
b/target/loongarch/insn_trans/trans_branch.c.inc
index 3ad34bcc05..2e35572cea 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -12,7 +12,7 @@ static bool trans_b(DisasContext *ctx, arg_b *a)
static bool trans_bl(DisasContext *ctx, arg_bl *a)
{
- tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4));
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
@@ -25,7 +25,7 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
TCGv addr = make_address_i(ctx, src1, a->imm);
tcg_gen_mov_tl(cpu_pc, addr);
- tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(dest, make_address_pc(ctx, ctx->base.pc_next + 4));
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
--
2.39.1
- [PATCH v4 00/15] Add some checks before translating instructions, Song Gao, 2023/08/21
- [PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode,
Song Gao <=
- [PATCH v4 01/15] target/loongarch: Support LoongArch32 TLB entry, Song Gao, 2023/08/21
- [PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode, Song Gao, 2023/08/21
- [PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext, Song Gao, 2023/08/21
- [PATCH v4 10/15] hw/loongarch: Remove restriction of la464 cores in the virt machine, Song Gao, 2023/08/21
- [PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132, Song Gao, 2023/08/21