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[PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext
From: |
Song Gao |
Subject: |
[PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext |
Date: |
Tue, 22 Aug 2023 11:27:13 +0800 |
From: Jiajie Chen <c@jia.je>
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.h | 13 +++++++++++++
target/loongarch/translate.h | 2 ++
target/loongarch/translate.c | 3 +++
3 files changed, 18 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index b8af491041..72109095e4 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -432,6 +432,17 @@ static inline bool is_la64(CPULoongArchState *env)
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
}
+static inline bool is_va32(CPULoongArchState *env)
+{
+ /* VA32 if !LA64 or VA32L[1-3] */
+ bool va32 = !is_la64(env);
+ uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
+ va32 = true;
+ }
+ return va32;
+}
+
/*
* LoongArch CPUs hardware flags.
*/
@@ -439,6 +450,7 @@ static inline bool is_la64(CPULoongArchState *env)
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
+#define HW_FLAGS_VA32 0x20
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
@@ -448,6 +460,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState
*env, vaddr *pc,
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+ *flags |= is_va32(env) * HW_FLAGS_VA32;
}
void loongarch_cpu_list(void);
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 7f60090580..b6fa5df82d 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -33,6 +33,8 @@ typedef struct DisasContext {
uint16_t plv;
int vl; /* Vector length */
TCGv zero;
+ bool la64; /* LoongArch64 mode */
+ bool va32; /* 32-bit virtual address */
} DisasContext;
void generate_exception(DisasContext *ctx, int excp);
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3146a2d4ac..ac847745df 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -119,6 +119,9 @@ static void
loongarch_tr_init_disas_context(DisasContextBase *dcbase,
ctx->vl = LSX_LEN;
}
+ ctx->la64 = is_la64(env);
+ ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
+
ctx->zero = tcg_constant_tl(0);
}
--
2.39.1
- [PATCH v4 00/15] Add some checks before translating instructions, Song Gao, 2023/08/21
- [PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode, Song Gao, 2023/08/21
- [PATCH v4 01/15] target/loongarch: Support LoongArch32 TLB entry, Song Gao, 2023/08/21
- [PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode, Song Gao, 2023/08/21
- [PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext,
Song Gao <=
- [PATCH v4 10/15] hw/loongarch: Remove restriction of la464 cores in the virt machine, Song Gao, 2023/08/21
- [PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132, Song Gao, 2023/08/21
- [PATCH v4 03/15] target/loongarch: Support LoongArch32 VPPN, Song Gao, 2023/08/21
- [PATCH v4 07/15] target/loongarch: Add a check parameter to the TRANS macro, Song Gao, 2023/08/21
- [PATCH v4 02/15] target/loongarch: Support LoongArch32 DMW, Song Gao, 2023/08/21
- [PATCH v4 13/15] target/loongarch: Add avail_LAM to check atomic instructions, Song Gao, 2023/08/21