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[PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations
From: |
Richard Henderson |
Subject: |
[PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations |
Date: |
Fri, 13 Oct 2023 14:28:14 -0700 |
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/helper.h | 3 +--
target/sparc/fop_helper.c | 17 ++--------------
target/sparc/translate.c | 42 ++++++++++++---------------------------
3 files changed, 16 insertions(+), 46 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index b8f1e78c75..a9ee8e6b9f 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -43,7 +43,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int,
i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
-DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
+DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
@@ -55,7 +55,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
-DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64)
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
index f54fa9b959..0f8aa3abcd 100644
--- a/target/sparc/fop_helper.c
+++ b/target/sparc/fop_helper.c
@@ -382,20 +382,7 @@ static void set_fsr(CPUSPARCState *env, target_ulong fsr)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
-target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
- uint32_t new_fsr)
+void helper_set_fsr(CPUSPARCState *env, target_ulong fsr)
{
- old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
- set_fsr(env, old_fsr);
- return old_fsr;
+ set_fsr(env, fsr);
}
-
-#ifdef TARGET_SPARC64
-target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
- uint64_t new_fsr)
-{
- old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
- set_fsr(env, old_fsr);
- return old_fsr;
-}
-#endif
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 9384815f0b..6598557bb5 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -58,7 +58,8 @@
#define gen_helper_retry(E) qemu_build_not_reached()
#define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
#define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
-#define gen_helper_ldxfsr(R, E, X, Y) qemu_build_not_reached()
+#define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; })
+#define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; })
# ifdef CONFIG_USER_ONLY
static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
TCGv_i32 asi, TCGv_i32 mop)
@@ -4697,44 +4698,27 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
return true;
}
-static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)
+static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop,
+ target_ulong new_mask, target_ulong old_mask)
{
- TCGv addr;
- TCGv_i32 tmp;
-
- addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
+ TCGv tmp, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
if (addr == NULL) {
return false;
}
if (gen_trap_ifnofpu(dc)) {
return true;
}
- tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN);
- gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp);
+ tmp = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN);
+ tcg_gen_andi_tl(tmp, tmp, new_mask);
+ tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask);
+ tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp);
+ gen_helper_set_fsr(tcg_env, cpu_fsr);
return advance_pc(dc);
}
-static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a)
-{
- TCGv addr;
- TCGv_i64 tmp;
-
- if (!avail_64(dc)) {
- return false;
- }
- addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
- if (addr == NULL) {
- return false;
- }
- if (gen_trap_ifnofpu(dc)) {
- return true;
- }
- tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN);
- gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp);
- return advance_pc(dc);
-}
+TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK)
+TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMASK)
static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
{
--
2.34.1
- [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed, (continued)
- [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/13
- [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/13
- [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 51/85] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 47/85] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 52/85] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations,
Richard Henderson <=
- [PATCH 54/85] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 56/85] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 57/85] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/13
- [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}*, Richard Henderson, 2023/10/13
- [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/13
- [PATCH 55/85] target/sparc: Move ARRAY* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree, Richard Henderson, 2023/10/13
- [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 68/85] target/sparc: Move gen_fop_FFF insns to decodetree, Richard Henderson, 2023/10/13