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[PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}*
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From: |
Richard Henderson |
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Subject: |
[PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}* |
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Date: |
Fri, 13 Oct 2023 14:28:21 -0700 |
Replace the local helpers for the same integer operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/helper.h | 12 --------
target/sparc/translate.c | 15 +++++-----
target/sparc/vis_helper.c | 59 ---------------------------------------
3 files changed, 7 insertions(+), 79 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index a9ee8e6b9f..8d20258d08 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -138,18 +138,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64,
i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
-#define VIS_HELPER(name) \
- DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE, \
- i64, i64, i64) \
- DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \
- i32, i32, i32) \
- DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE, \
- i64, i64, i64) \
- DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \
- i32, i32, i32)
-
-VIS_HELPER(padd)
-VIS_HELPER(psub)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0a1ebb62e3..3b6f4bef95 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -25,9 +25,8 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
-
+#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
-
#include "exec/translator.h"
#include "exec/log.h"
#include "asi.h"
@@ -5337,15 +5336,15 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
break;
case 0x050: /* VIS I fpadd16 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
+ gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64);
break;
case 0x051: /* VIS I fpadd16s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
+ gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32);
break;
case 0x052: /* VIS I fpadd32 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
+ gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
break;
case 0x053: /* VIS I fpadd32s */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -5353,15 +5352,15 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
break;
case 0x054: /* VIS I fpsub16 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
+ gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64);
break;
case 0x055: /* VIS I fpsub16s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
+ gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32);
break;
case 0x056: /* VIS I fpsub32 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
+ gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
break;
case 0x057: /* VIS I fpsub32s */
CHECK_FPU_FEATURE(dc, VIS1);
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 3afdc6975c..7763b16c24 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
return d.ll;
}
-#define VIS_HELPER(name, F) \
- uint64_t name##16(uint64_t src1, uint64_t src2) \
- { \
- VIS64 s, d; \
- \
- s.ll = src1; \
- d.ll = src2; \
- \
- d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
- d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
- d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
- d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
- \
- return d.ll; \
- } \
- \
- uint32_t name##16s(uint32_t src1, uint32_t src2) \
- { \
- VIS32 s, d; \
- \
- s.l = src1; \
- d.l = src2; \
- \
- d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
- d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
- \
- return d.l; \
- } \
- \
- uint64_t name##32(uint64_t src1, uint64_t src2) \
- { \
- VIS64 s, d; \
- \
- s.ll = src1; \
- d.ll = src2; \
- \
- d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
- d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
- \
- return d.ll; \
- } \
- \
- uint32_t name##32s(uint32_t src1, uint32_t src2) \
- { \
- VIS32 s, d; \
- \
- s.l = src1; \
- d.l = src2; \
- \
- d.l = F(d.l, s.l); \
- \
- return d.l; \
- }
-
-#define FADD(a, b) ((a) + (b))
-#define FSUB(a, b) ((a) - (b))
-VIS_HELPER(helper_fpadd, FADD)
-VIS_HELPER(helper_fpsub, FSUB)
-
#define VIS_CMPHELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
--
2.34.1
- [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree, (continued)
- [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 51/85] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 47/85] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 52/85] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations, Richard Henderson, 2023/10/13
- [PATCH 54/85] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 56/85] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 57/85] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/13
- [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}*,
Richard Henderson <=
- [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/13
- [PATCH 55/85] target/sparc: Move ARRAY* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree, Richard Henderson, 2023/10/13
- [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 68/85] target/sparc: Move gen_fop_FFF insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree, Richard Henderson, 2023/10/13
- [PATCH 66/85] target/sparc: Move gen_fop_DD insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 67/85] target/sparc: Move FSQRTq to decodetree, Richard Henderson, 2023/10/13
- [PATCH 69/85] target/sparc: Move gen_fop_DDD insns to decodetree, Richard Henderson, 2023/10/13