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[PULL 51/65] target/riscv: add satp_mode profile support
From: |
Alistair Francis |
Subject: |
[PULL 51/65] target/riscv: add satp_mode profile support |
Date: |
Wed, 10 Jan 2024 18:57:19 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
'satp_mode' is a requirement for supervisor profiles like RVA22S64.
User-mode/application profiles like RVA22U64 doesn't care.
Add 'satp_mode' to the profile description. If a profile requires it,
set it during cpu_set_profile(). We'll also check it during finalize()
to validate if the running config implements the profile.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-24-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
target/riscv/tcg/tcg-cpu.c | 40 ++++++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a0f768e77d..136030434e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,6 +82,7 @@ typedef struct riscv_cpu_profile {
bool enabled;
bool user_set;
int priv_spec;
+ int satp_mode;
const int32_t ext_offsets[];
} RISCVCPUProfile;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4d1fd7fd48..1aeb0fee1b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1542,6 +1542,7 @@ static RISCVCPUProfile RVA22U64 = {
.name = "rva22u64",
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
+ .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
.ext_offsets = {
CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 41eef87e6e..a0a3350e3e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -771,6 +771,31 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
riscv_cpu_disable_priv_spec_isa_exts(cpu);
}
+#ifndef CONFIG_USER_ONLY
+static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
+ RISCVCPUProfile *profile,
+ bool send_warn)
+{
+ int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
+
+ if (profile->satp_mode > satp_max) {
+ if (send_warn) {
+ bool is_32bit = riscv_cpu_is_32bit(cpu);
+ const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit);
+ const char *cur_satp = satp_mode_str(satp_max, is_32bit);
+
+ warn_report("Profile %s requires satp mode %s, "
+ "but satp mode %s was set", profile->name,
+ req_satp, cur_satp);
+ }
+
+ return false;
+ }
+
+ return true;
+}
+#endif
+
static void riscv_cpu_validate_profile(RISCVCPU *cpu,
RISCVCPUProfile *profile)
{
@@ -780,6 +805,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
bool profile_impl = true;
int i;
+#ifndef CONFIG_USER_ONLY
+ if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
+ profile_impl = riscv_cpu_validate_profile_satp(cpu, profile,
+ send_warn);
+ }
+#endif
+
if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
profile->priv_spec != env->priv_ver) {
profile_impl = false;
@@ -1084,6 +1116,14 @@ static void cpu_set_profile(Object *obj, Visitor *v,
const char *name,
cpu->env.priv_ver = profile->priv_spec;
}
+#ifndef CONFIG_USER_ONLY
+ if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
+ const char *satp_prop = satp_mode_str(profile->satp_mode,
+ riscv_cpu_is_32bit(cpu));
+ object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
+ }
+#endif
+
for (i = 0; misa_bits[i] != 0; i++) {
uint32_t bit = misa_bits[i];
--
2.43.0
- [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits, (continued)
- [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits, Alistair Francis, 2024/01/10
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, Alistair Francis, 2024/01/10
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Alistair Francis, 2024/01/10
- [PULL 46/65] target/riscv: add 'rva22u64' CPU, Alistair Francis, 2024/01/10
- [PULL 47/65] target/riscv: implement svade, Alistair Francis, 2024/01/10
- [PULL 48/65] target/riscv: add priv ver restriction to profiles, Alistair Francis, 2024/01/10
- [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier, Alistair Francis, 2024/01/10
- [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit(), Alistair Francis, 2024/01/10
- [PULL 51/65] target/riscv: add satp_mode profile support,
Alistair Francis <=
- [PULL 52/65] target/riscv: add 'parent' in profile description, Alistair Francis, 2024/01/10
- [PULL 53/65] target/riscv: add RVA22S64 profile, Alistair Francis, 2024/01/10
- [PULL 54/65] target/riscv: add rva22s64 cpu, Alistair Francis, 2024/01/10
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10