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[Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction |
Date: |
Fri, 7 Mar 2014 00:33:16 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c9aebc5..951f15e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3508,6 +3508,20 @@ static void gen_lfiwax(DisasContext *ctx)
tcg_temp_free(t0);
}
+/* lfiwzx */
+static void gen_lfiwzx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_temp_free(EA);
+}
/*** Floating-point store ***/
#define GEN_STF(name, stop, opc, type) \
static void glue(gen_, name)(DisasContext *ctx)
\
@@ -9984,6 +9998,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
--
1.8.1.4
- [Qemu-ppc] [PULL 011/130] mmu-hash64: fix Virtual Page Class Key Protection, (continued)
- [Qemu-ppc] [PULL 011/130] mmu-hash64: fix Virtual Page Class Key Protection, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 021/130] target-ppc: Add VSX ISA2.06 xdiv Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 031/130] target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 032/130] target-ppc: Add VSX ISA2.06 Integer Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction,
Alexander Graf <=
- [Qemu-ppc] [PULL 054/130] target-ppc: Add ISA2.06 divdeu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 061/130] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 071/130] virtex_ml507: Add support for loading initrd images, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 060/130] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 070/130] PPC: KVM: store SLB slot number, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 065/130] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 062/130] target-ppc: Add ISA2.06 Float to Integer Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 074/130] spapr: support only ELF kernel images, Alexander Graf, 2014/03/06