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[Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions |
Date: |
Fri, 7 Mar 2014 00:32:55 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vector instructions if the
indexed VSR is in the second half of the array (32-63).
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 19b6756..bc608ee 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7175,6 +7175,57 @@ static void gen_stxvw4x(DisasContext *ctx)
tcg_temp_free_i64(tmp);
}
+#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ if (xS(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ TCGv_i64 tmp = tcg_temp_new_i64(); \
+ tcg_gen_##tcgop1(tmp, source); \
+ tcg_gen_##tcgop2(target, tmp); \
+ tcg_temp_free_i64(tmp); \
+}
+
+
+MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
+ cpu_vsrh(xS(ctx->opcode)))
+MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
+ cpu_gpr[rA(ctx->opcode)])
+MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
+ cpu_gpr[rA(ctx->opcode)])
+
+#if defined(TARGET_PPC64)
+#define MV_VSRD(name, target, source) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ if (xS(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ tcg_gen_mov_i64(target, source); \
+}
+
+MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
+MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
+
+#endif
+
static void gen_xxpermdi(DisasContext *ctx)
{
if (unlikely(!ctx->vsx_enabled)) {
@@ -10094,6 +10145,14 @@ GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE,
PPC2_VSX207),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
+#endif
+
#undef GEN_XX2FORM
#define GEN_XX2FORM(name, opc2, opc3, fl2) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
--
1.8.1.4
- [Qemu-ppc] [PULL 016/130] target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL, (continued)
- [Qemu-ppc] [PULL 016/130] target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 014/130] spapr-pci: enable adding PHB via -device, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 012/130] PPC: KVM: fix "set one register", Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 027/130] target-ppc: Add VSX ISA2.06 Multiply Add Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 019/130] target-ppc: Add VSX ISA2.06 xadd/xsub Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 011/130] mmu-hash64: fix Virtual Page Class Key Protection, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 021/130] target-ppc: Add VSX ISA2.06 xdiv Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 004/130] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 031/130] target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 032/130] target-ppc: Add VSX ISA2.06 Integer Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions,
Alexander Graf <=
- [Qemu-ppc] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 054/130] target-ppc: Add ISA2.06 divdeu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 061/130] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 071/130] virtex_ml507: Add support for loading initrd images, Alexander Graf, 2014/03/06