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[Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable in
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts |
Date: |
Tue, 6 Sep 2016 13:42:43 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This is no longer necessary as the helpers will properly retrieve
the return address when needed. Also remove gen_update_current_nip()
which didn't seem to make much sense to me.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 1 -
target-ppc/misc_helper.c | 9 +++++----
target-ppc/translate.c | 7 -------
target-ppc/translate_init.c | 2 --
4 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a872efb..1e808c8 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1202,7 +1202,6 @@ extern const struct VMStateDescription vmstate_ppc_cpu;
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
void ppc_translate_init(void);
const char *ppc_cpu_lookup_alias(const char *alias);
-void gen_update_current_nip(void *opaque);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index cb5ebf5..1e6e705 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -39,7 +39,8 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
#ifdef TARGET_PPC64
static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
- uint32_t sprn, uint32_t cause)
+ uint32_t sprn, uint32_t cause,
+ uintptr_t raddr)
{
qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
@@ -47,7 +48,7 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
cause &= FSCR_IC_MASK;
env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
- helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
+ raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
}
#endif
@@ -59,7 +60,7 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t
bit,
/* Facility is enabled, continue */
return;
}
- raise_fu_exception(env, bit, sprn, cause);
+ raise_fu_exception(env, bit, sprn, cause, GETPC());
#endif
}
@@ -71,7 +72,7 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
/* Facility is enabled, continue */
return;
}
- raise_fu_exception(env, bit, sprn, cause);
+ raise_fu_exception(env, bit, sprn, cause, GETPC());
#endif
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 46b0e18..b62772b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -266,13 +266,6 @@ static inline void gen_update_nip(DisasContext *ctx,
target_ulong nip)
tcg_gen_movi_tl(cpu_nip, nip);
}
-void gen_update_current_nip(void *opaque)
-{
- DisasContext *ctx = opaque;
-
- tcg_gen_movi_tl(cpu_nip, ctx->nip);
-}
-
static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
{
TCGv_i32 t0, t1;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4768b43..3993994 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7470,7 +7470,6 @@ static void gen_fscr_facility_check(DisasContext *ctx,
int facility_sprn,
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
- gen_update_current_nip(ctx);
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
tcg_temp_free_i32(t3);
@@ -7485,7 +7484,6 @@ static void gen_msr_facility_check(DisasContext *ctx, int
facility_sprn,
TCGv_i32 t2 = tcg_const_i32(sprn);
TCGv_i32 t3 = tcg_const_i32(cause);
- gen_update_current_nip(ctx);
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
tcg_temp_free_i32(t3);
--
2.7.4
- [Qemu-ppc] [PULL 55/66] hw/ppc: use error_report instead of fprintf, (continued)
- [Qemu-ppc] [PULL 55/66] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 58/66] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 54/66] ppc: Rename #include'd .c files to .inc.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 07/66] target-ppc: add modulo word operations, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 60/66] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 17/66] ppc: Move classic fp ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 05/66] target-ppc: adding addpcis instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 26/66] ppc: FP exceptions are always precise, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts,
David Gibson <=
- [Qemu-ppc] [PULL 13/66] target-ppc: add maddld instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 11/66] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 29/66] ppc: Make tlb_fill() use new exception helper, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 25/66] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 22/66] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 40/66] ppc: Speed up dcbz, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 30/66] ppc: Rework NIP updates vs. exception generation, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 47/66] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/05