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[Qemu-ppc] [PATCH 11/12] target/ppc: Support for POWER9 native hash
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 11/12] target/ppc: Support for POWER9 native hash |
Date: |
Fri, 15 Feb 2019 18:00:28 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
(Might need more patch splitting)
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
target/ppc/mmu-book3s-v3.h | 45 ++++++++++++++++++++++++++++++++++++++
target/ppc/mmu-hash64.h | 19 +---------------
target/ppc/mmu-book3s-v3.c | 18 +++++++++++++++
target/ppc/mmu-hash64.c | 6 +++--
4 files changed, 68 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index 8474dfec41d9..f423d51f68ab 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -55,6 +55,9 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
}
+bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
+ ppc_v3_pate_t *entry);
+
/*
* The LPCR:HR bit is a shortcut that avoids having to
* dig out the partition table in the fast path. This is
@@ -82,6 +85,48 @@ hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr
eaddr);
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx);
+static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
+{
+ uint64_t base;
+
+ if (cpu->vhyp) {
+ return 0;
+ }
+ if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
+ ppc_v3_pate_t pate;
+
+ if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
+ return 0;
+ }
+ base = pate.dw0;
+ } else {
+ base = cpu->env.spr[SPR_SDR1];
+ }
+ return base & SDR_64_HTABORG;
+}
+
+static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
+{
+ uint64_t base;
+
+ if (cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ return vhc->hpt_mask(cpu->vhyp);
+ }
+ if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
+ ppc_v3_pate_t pate;
+
+ if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
+ return 0;
+ }
+ base = pate.dw0;
+ } else {
+ base = cpu->env.spr[SPR_SDR1];
+ }
+ return (1ULL << ((base & SDR_64_HTABSIZE) + 18 - 7)) - 1;
+}
+
#endif /* TARGET_PPC64 */
#endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 016d6b44ee75..6b555b72200f 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -63,6 +63,7 @@ void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
#define SDR_64_HTABSIZE 0x000000000000001FULL
+#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
#define HPTES_PER_GROUP 8
#define HASH_PTE_SIZE_64 16
#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
@@ -107,24 +108,6 @@ void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
#define HPTE64_R_3_0_SSIZE_SHIFT 58
#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
-static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
-{
- if (cpu->vhyp) {
- return 0;
- }
- return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
-}
-
-static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
-{
- if (cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- return vhc->hpt_mask(cpu->vhyp);
- }
- return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
-}
-
struct ppc_hash_pte64 {
uint64_t pte0, pte1;
};
diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index ccbae3213cc1..400529d683cf 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -39,3 +39,21 @@ hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr
eaddr)
return ppc_hash64_get_phys_page_debug(cpu, eaddr);
}
}
+
+bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t
*entry)
+{
+ uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB;
+ uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
+
+ /* Calculate number of entries */
+ pats = 1ull << (pats + 12 - 4);
+ if (pats <= lpid) {
+ return false;
+ }
+
+ /* Grab entry */
+ patb += 16 * lpid;
+ entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
+ entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return true;
+}
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 9afaab8a177c..a401f257a34f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -416,7 +416,7 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU
*cpu,
hwaddr ptex, int n)
{
hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
- hwaddr base = ppc_hash64_hpt_base(cpu);
+ hwaddr base;
hwaddr plen = n * HASH_PTE_SIZE_64;
const ppc_hash_pte64_t *hptes;
@@ -425,6 +425,7 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU
*cpu,
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
return vhc->map_hptes(cpu->vhyp, ptex, n);
}
+ base = ppc_hash64_hpt_base(cpu);
if (!base) {
return NULL;
@@ -928,7 +929,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong addr)
void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
uint64_t pte0, uint64_t pte1)
{
- hwaddr base = ppc_hash64_hpt_base(cpu);
+ hwaddr base;
hwaddr offset = ptex * HASH_PTE_SIZE_64;
if (cpu->vhyp) {
@@ -937,6 +938,7 @@ void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1);
return;
}
+ base = ppc_hash64_hpt_base(cpu);
stq_phys(CPU(cpu)->as, base + offset, pte0);
stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1);
--
2.20.1
- [Qemu-ppc] [PATCH 00/12] ppc: add native hash and radix support for POWER9, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 10/12] target/ppc: Rename PATB/PATBE -> PATE, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 03/12] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 11/12] target/ppc: Support for POWER9 native hash,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH 07/12] target/ppc: Add basic support for "new format" HPTE as found on POWER9, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 05/12] target/ppc: Cleanup 64-bit MMU includes, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 08/12] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 12/12] target/ppc: Basic POWER9 bare-metal radix MMU support, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPIDR is written, Cédric Le Goater, 2019/02/15
- [Qemu-ppc] [PATCH 01/12] target/ppc/spapr: Set LPCR:HR when using Radix mode, Cédric Le Goater, 2019/02/15