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[Qemu-ppc] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system |
Date: |
Wed, 18 Sep 2019 18:06:30 +0200 |
The TIMA MMIO space is shared among the chips. To identify the chip
from which the access is being done, the PowerBUS uses a 'chip' field
in the load/store messages. QEMU does not model these messages,
instead, we extract the chip id from the CPU PIR and do a lookup at
the machine level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
this process in pnv_xive_get_tctx(). The latter will be removed in the
subsequent patches but the same principle will be kept.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/pnv.h | 13 +++++++++++++
hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
2 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 1cdbe55bf86c..5e01a9f3df95 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -185,6 +185,19 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
return pnv_chip_is_power9(pnv->chips[0]);
}
+static inline PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
+{
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ PnvChip *chip = pnv->chips[i];
+ if (chip->chip_id == chip_id) {
+ return chip;
+ }
+ }
+ return NULL;
+}
+
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 5c9483b394ab..3d6fcf9ac139 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -464,31 +464,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr,
uint8_t format,
return count;
}
+/*
+ * The TIMA MMIO space is shared among the chips and to identify the
+ * chip from which the access is being done, we extract the chip id
+ * from the PIR.
+ */
+static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvChip *chip;
+ PnvXive *xive;
+
+ chip = pnv_get_chip(pnv, cpu_chip_id(cpu));
+ assert(chip);
+ xive = &PNV9_CHIP(chip)->xive;
+
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ xive_error(xive, "IC: CPU %x is not enabled", cpu_pir(cpu));
+ }
+ return xive;
+}
+
static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- PnvXive *xive = NULL;
- CPUPPCState *env = &cpu->env;
- int pir = env->spr_cb[SPR_PIR].default_value;
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
- /*
- * Perform an extra check on the HW thread enablement.
- *
- * The TIMA is shared among the chips and to identify the chip
- * from which the access is being done, we extract the chip id
- * from the PIR.
- */
- xive = pnv_xive_get_ic((pir >> 8) & 0xf);
if (!xive) {
return NULL;
}
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
- xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
- }
-
- return tctx;
+ return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
}
/*
--
2.21.0
- [Qemu-ppc] [PATCH v4 00/25] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 01/25] ppc/xive: Introduce a XivePresenter interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 02/25] ppc/xive: Implement the XivePresenter interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 04/25] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 06/25] ppc/pnv: Implement the XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 07/25] ppc/spapr: Implement the XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v4 11/25] ppc/xive: Move the TIMA operations to the controller model, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 18/25] ppc/pnv: Skip empty slots of the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler, Cédric Le Goater, 2019/09/18