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[Qemu-ppc] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the save
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT |
Date: |
Wed, 18 Sep 2019 18:06:35 +0200 |
When an interrupt can not be presented to a vCPU, the XIVE presenter
updates the Interrupt Pending Buffer of the XIVE NVT if backlog is
activated in the END.
Later, when the same vCPU is dispatched, its context is pushed in the
thread context registers and the VO bit is set in the CAM line word to
activate the context. The HW grabs the associated NVT to pull the
pending bits, and merges them with the IPB of the TIMA. If interrupts
were missed while the vCPU was not dispatched, these are synthesized
in this sequence.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 67 +++++++++++++++++++++++++++++++++-----
2 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 3d7b6fd09664..dea0318e7e89 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -235,6 +235,7 @@ typedef struct XiveNVT {
uint32_t w2;
uint32_t w3;
uint32_t w4;
+#define NVT_W4_IPB PPC_BITMASK32(16, 23)
uint32_t w5;
uint32_t w6;
uint32_t w7;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 5f7c37b091a7..f47b0cf2b053 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
}
-static void ipb_update(uint8_t *regs, uint8_t priority)
-{
- regs[TM_IPB] |= priority_to_ipb(priority);
- regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
-}
-
static uint8_t exception_mask(uint8_t ring)
{
switch (ring) {
@@ -359,6 +353,55 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr,
XiveTCTX *tctx,
return qw1w2;
}
+static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+ uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ XiveNVT nvt;
+ uint8_t ipb;
+
+ /*
+ * Grab the associated NVT to pull the pending bits, and merge
+ * them with the IPB of the thread interrupt context registers
+ */
+ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
+
+ if (ipb) {
+ /* Reset the NVT value */
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
+ xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ /* Merge in current context */
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t qw1w2 = value;
+ uint8_t nvt_blk = xive_nvt_blk(qw1w2);
+ uint32_t nvt_idx = xive_nvt_idx(qw1w2);
+ bool vo = !!(qw1w2 & TM_QW1W2_VO);
+
+ /* First update the registers */
+ qw1w2 = cpu_to_be32(qw1w2);
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ }
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -380,6 +423,7 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL
},
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL
},
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
@@ -1523,14 +1567,21 @@ static void xive_router_end_notify(XiveRouter *xrtr,
uint8_t end_blk,
* - logical server : forward request to IVPE (not supported)
*/
if (xive_end_is_backlog(&end)) {
+ uint8_t ipb;
+
if (format == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"XIVE: END %x/%x invalid config: F1 & backlog\n",
end_blk, end_idx);
return;
}
- /* Record the IPB in the associated NVT structure */
- ipb_update((uint8_t *) &nvt.w4, priority);
+ /*
+ * Record the IPB in the associated NVT structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority);
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
/*
--
2.21.0
- [Qemu-ppc] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface, (continued)
- [Qemu-ppc] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 06/25] ppc/pnv: Implement the XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 07/25] ppc/spapr: Implement the XiveFabric interface, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 11/25] ppc/xive: Move the TIMA operations to the controller model, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 18/25] ppc/pnv: Skip empty slots of the XIVE NVT table, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition, Cédric Le Goater, 2019/09/18
- [Qemu-ppc] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI, Cédric Le Goater, 2019/09/18