[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registra
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registration |
Date: |
Fri, 7 Jul 2023 08:30:45 -0300 |
From: BALATON Zoltan <balaton@eik.bme.hu>
It is shorter and more readable to wrap the complex call to
ppc_dcr_register() in a macro than to repeat it several times.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<4dec5ef8115791dc67253afdff9a703eb816a2a8.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/ppc440_uc.c | 76 +++++++++++++++++-----------------------------
1 file changed, 28 insertions(+), 48 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index b26c0cee1b..b36dc409d7 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -1002,56 +1002,36 @@ static void ppc460ex_set_irq(void *opaque, int irq_num,
int level)
qemu_set_irq(s->irq[irq_num], level);
}
+#define PPC440_PCIE_DCR(s, dcrn) \
+ ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
+ &dcr_read_pcie, &dcr_write_pcie)
+
+
static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s)
{
- CPUPPCState *env = &s->cpu->env;
-
- ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s,
- &dcr_read_pcie, &dcr_write_pcie);
- ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s,
- &dcr_read_pcie, &dcr_write_pcie);
+ PPC440_PCIE_DCR(s, PEGPL_CFGBAH);
+ PPC440_PCIE_DCR(s, PEGPL_CFGBAL);
+ PPC440_PCIE_DCR(s, PEGPL_CFGMSK);
+ PPC440_PCIE_DCR(s, PEGPL_MSGBAH);
+ PPC440_PCIE_DCR(s, PEGPL_MSGBAL);
+ PPC440_PCIE_DCR(s, PEGPL_MSGMSK);
+ PPC440_PCIE_DCR(s, PEGPL_OMR1BAH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR1BAL);
+ PPC440_PCIE_DCR(s, PEGPL_OMR1MSKH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR1MSKL);
+ PPC440_PCIE_DCR(s, PEGPL_OMR2BAH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR2BAL);
+ PPC440_PCIE_DCR(s, PEGPL_OMR2MSKH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR2MSKL);
+ PPC440_PCIE_DCR(s, PEGPL_OMR3BAH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR3BAL);
+ PPC440_PCIE_DCR(s, PEGPL_OMR3MSKH);
+ PPC440_PCIE_DCR(s, PEGPL_OMR3MSKL);
+ PPC440_PCIE_DCR(s, PEGPL_REGBAH);
+ PPC440_PCIE_DCR(s, PEGPL_REGBAL);
+ PPC440_PCIE_DCR(s, PEGPL_REGMSK);
+ PPC440_PCIE_DCR(s, PEGPL_SPECIAL);
+ PPC440_PCIE_DCR(s, PEGPL_CFG);
}
static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
--
2.41.0
- [PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages, (continued)
- [PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages, Daniel Henrique Barboza, 2023/07/07
- [PULL 28/60] ppc/pegasos2: Add support for -initrd command line option, Daniel Henrique Barboza, 2023/07/07
- [PULL 29/60] pnv/xive: Print CPU target in all TIMA traces, Daniel Henrique Barboza, 2023/07/07
- [PULL 30/60] pnv/xive2: Always pass a presenter object when accessing the TIMA, Daniel Henrique Barboza, 2023/07/07
- [PULL 31/60] target/ppc: Add LPAR-per-core vs per-thread mode flag, Daniel Henrique Barboza, 2023/07/07
- [PULL 32/60] target/ppc: SMT support for the HID SPR, Daniel Henrique Barboza, 2023/07/07
- [PULL 33/60] ppc/pnv: SMT support for powernv, Daniel Henrique Barboza, 2023/07/07
- [PULL 34/60] tests/avocado: Add powernv machine test script, Daniel Henrique Barboza, 2023/07/07
- [PULL 35/60] ppc440: Change ppc460ex_pcie_init() parameter type, Daniel Henrique Barboza, 2023/07/07
- [PULL 36/60] ppc440: Add cpu link property to PCIe controller model, Daniel Henrique Barboza, 2023/07/07
- [PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registration,
Daniel Henrique Barboza <=
- [PULL 38/60] ppc440: Rename parent field of PPC460EXPCIEState to match code style, Daniel Henrique Barboza, 2023/07/07
- [PULL 40/60] ppc440: Stop using system io region for PCIe buses, Daniel Henrique Barboza, 2023/07/07
- [PULL 41/60] ppc440: Add busnum property to PCIe controller model, Daniel Henrique Barboza, 2023/07/07
- [PULL 39/60] ppc440: Rename local variable in dcr_read_pcie(), Daniel Henrique Barboza, 2023/07/07
- [PULL 43/60] ppc/sam460ex: Remove address_space_mem local variable, Daniel Henrique Barboza, 2023/07/07
- [PULL 44/60] ppc440_pcix: Don't use iomem for regs, Daniel Henrique Barboza, 2023/07/07
- [PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function, Daniel Henrique Barboza, 2023/07/07
- [PULL 45/60] ppc440_pcix: Stop using system io region for PCI bus, Daniel Henrique Barboza, 2023/07/07
- [PULL 46/60] ppc4xx_pci: Rename QOM type name define, Daniel Henrique Barboza, 2023/07/07
- [PULL 47/60] ppc4xx_pci: Add define for ppc4xx-host-bridge type name, Daniel Henrique Barboza, 2023/07/07