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[PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing
From: |
Nicholas Piggin |
Subject: |
[PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing |
Date: |
Mon, 19 Feb 2024 18:29:34 +1000 |
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu_helper.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index c140f3c96d..949ae87f4f 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -749,12 +749,20 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env,
target_ulong entry)
return ret;
}
+static void ppcemb_tlb_flush(CPUState *cs, ppcemb_tlb_t *tlb)
+{
+ target_ulong ea;
+
+ for (ea = tlb->EPN; ea < tlb->EPN + tlb->size; ea += TARGET_PAGE_SIZE) {
+ tlb_flush_page(cs, ea);
+ }
+}
+
void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
target_ulong val)
{
CPUState *cs = env_cpu(env);
ppcemb_tlb_t *tlb;
- target_ulong page, end;
qemu_log_mask(CPU_LOG_MMU, "%s entry %d val " TARGET_FMT_lx "\n",
__func__, (int)entry,
@@ -763,13 +771,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
entry,
tlb = &env->tlb.tlbe[entry];
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
- end = tlb->EPN + tlb->size;
qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start "
TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
- (int)entry, tlb->EPN, end);
- for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(cs, page);
- }
+ (int)entry, tlb->EPN, tlb->EPN + tlb->size);
+ ppcemb_tlb_flush(cs, tlb);
}
tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
& PPC4XX_TLBHI_SIZE_MASK);
@@ -805,13 +810,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
entry,
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
- end = tlb->EPN + tlb->size;
qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start "
TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
- (int)entry, tlb->EPN, end);
- for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(cs, page);
- }
+ (int)entry, tlb->EPN, tlb->EPN + tlb->size);
+ ppcemb_tlb_flush(cs, tlb);
}
}
--
2.42.0
- [PULL 38/49] target/ppc: Fix move-to timebase SPR access permissions, (continued)
- [PULL 38/49] target/ppc: Fix move-to timebase SPR access permissions, Nicholas Piggin, 2024/02/19
- [PULL 36/49] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/02/19
- [PULL 35/49] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/02/19
- [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/02/19
- [PULL 37/49] target/ppc: Improve timebase register defines naming, Nicholas Piggin, 2024/02/19
- [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/19
- [PULL 43/49] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/02/19
- [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/02/19
- [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/02/19
- [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps, Nicholas Piggin, 2024/02/19
- [PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing,
Nicholas Piggin <=
- [PULL 46/49] target/ppc: 4xx don't flush TLB for a newly written software TLB entry, Nicholas Piggin, 2024/02/19
- [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/19
- [PULL 48/49] target/ppc: 440 optimise tlbwe TLB flushing, Nicholas Piggin, 2024/02/19
- [PULL 47/49] target/ppc: 4xx optimise tlbwe_lo TLB flushing, Nicholas Piggin, 2024/02/19
- Re: [PULL 00/49] ppc-for-9.0 queue, Peter Maydell, 2024/02/19