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Re: [PULL 00/49] ppc-for-9.0 queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/49] ppc-for-9.0 queue |
Date: |
Mon, 19 Feb 2024 17:06:26 +0000 |
On Mon, 19 Feb 2024 at 08:31, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c:
>
> Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging
> (2024-02-16 11:05:14 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219
>
> for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1:
>
> target/ppc: optimise ppcemb_tlb_t flushing (2024-02-19 18:09:19 +1000)
>
> ----------------------------------------------------------------
> * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated
> or nested hypervisor facilities, among other things.
> * Update ppc64 CPU defaults to Power10.
> * Add a new powernv10-rainier machine to better capture differences
> between the different Power10 systems.
> * Implement more device models for powernv.
> * 4xx TLB flushing performance and correctness improvements.
> * Correct gdb implementation to access some important SPRs.
> * Misc cleanups and bug fixes.
>
> I dropped the BHRB patches, they are very close but minor issue only
> noticed recently held them up. Hopefully we can get those and a bunch
> of other outstanding submissions in for 9.0 but this PR was taking too
> long as it was.
> Peter Maydell (1):
> hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned
> accesses
Hi Nick -- this commit went upstream via a different route, and
so it now appears in this pullrequest as a commit with a commit
message but no contents. Could I ask you to respin the pullreq
with that commit dropped, please?
thanks
-- PMM
- [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model, (continued)
- [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/19
- [PULL 43/49] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/02/19
- [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/02/19
- [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/02/19
- [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps, Nicholas Piggin, 2024/02/19
- [PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/19
- [PULL 46/49] target/ppc: 4xx don't flush TLB for a newly written software TLB entry, Nicholas Piggin, 2024/02/19
- [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/19
- [PULL 48/49] target/ppc: 440 optimise tlbwe TLB flushing, Nicholas Piggin, 2024/02/19
- [PULL 47/49] target/ppc: 4xx optimise tlbwe_lo TLB flushing, Nicholas Piggin, 2024/02/19
- Re: [PULL 00/49] ppc-for-9.0 queue,
Peter Maydell <=